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From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: Vignesh Raghavendra <vigneshr-l0cyMroinI0@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	linux-spi <linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"Mark Brown" <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	simon.k.r.goldschmidt-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	"Dinh Nguyen" <dinguyen-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	tien.fong.chee-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
	"Marek Vašut" <marex-ynQEQJNshbs@public.gmane.org>,
	cheol.yong.kim-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
	qi-ming.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org
Subject: Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver
Date: Thu, 27 Feb 2020 13:59:16 +0800	[thread overview]
Message-ID: <d00e82c8-a8b2-6cb3-520b-7e78f81d0c41@linux.intel.com> (raw)
In-Reply-To: <22bb0c6c-db03-dee5-eccf-84b00216308f-l0cyMroinI0@public.gmane.org>

Hi,

On 27/2/2020 1:23 PM, Vignesh Raghavendra wrote:
>
> On 26/02/20 7:02 am, Ramuthevar, Vadivel MuruganX wrote:
>> Hi,
>>
>> On 25/2/2020 7:00 PM, Vignesh Raghavendra wrote:
>>> On 25/02/20 1:08 pm, Ramuthevar, Vadivel MuruganX wrote:
>>>>>>>> +
>>>>>>>> +  cdns,fifo-depth:
>>>>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>>>>> +    description:
>>>>>>>> +      Size of the data FIFO in words.
>>>>>>> A 4GB fifo is valid? Add some constraints.
>>>>>> 128 is valid, will update.
>>>>> Nope, the width of this field is 8bits -> 256 bytes
>>>> correct me if I am wrong, the width of this field is 4bits -> 128 bytes
>>>> (based on QUAD mode) .
>>> This has nothing to do with quad-mode. Its about how much SRAM amount of
>>> SRAM is present to buffer INDAC mode data. For TI platforms this is 256
>>> bytes.
>>> See CQSPI_REG_SRAMPARTITION definition in your datasheet.
>> Agreed, Thanks!
>> Yes , I have gone through it , Intel and Altera SoC's SRAM(act as
>> FIFO)size is 128 bytes and TI has 256 .
>> BTW old legacy DT binding mentioned size is 128, as per your earlier
>> suggestion you have mention that
>> keep the contents from old dt bindings as it is, so shall I keep 128/256?
> Old bindings does not impose a restriction that this needs to be 128
> bytes always (Its just the example that shows this property to be set to
> 128)
>
> What Rob is asking for is to add range of values that is valid for this
> field and not single value. So, both 128 and 256 bytes should be allowed
> as valid values for this property.

Thank you Vignesh, will add both.

Regards
Vadivel
>

  parent reply	other threads:[~2020-02-27  5:59 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-19  2:28 [PATCH v10 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
     [not found] ` <20200219022852.28065-1-vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-02-19  2:28   ` [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX
     [not found]     ` <20200219022852.28065-2-vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-02-24 15:54       ` Rob Herring
     [not found]         ` <CAL_JsqKJky=y4nhECUFVzTYvEpjFoOH_6UY9uZG5bvBVWq=SYQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2020-02-25  6:24           ` Ramuthevar, Vadivel MuruganX
     [not found]             ` <64b7ab12-0c11-df25-95e7-ee62227ec7ec-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-02-25  6:41               ` Vignesh Raghavendra
     [not found]                 ` <85178128-4906-8b1a-e3f1-ab7a36ff8c23-l0cyMroinI0@public.gmane.org>
2020-02-25  7:38                   ` Ramuthevar, Vadivel MuruganX
     [not found]                     ` <c119a70d-b7ef-ab1b-4590-7ac77395297f-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-02-25 11:00                       ` Vignesh Raghavendra
     [not found]                         ` <8c329860-84fd-463b-782f-83a788998878-l0cyMroinI0@public.gmane.org>
2020-02-26  1:32                           ` Ramuthevar, Vadivel MuruganX
2020-02-27  5:23                             ` Vignesh Raghavendra
     [not found]                               ` <22bb0c6c-db03-dee5-eccf-84b00216308f-l0cyMroinI0@public.gmane.org>
2020-02-27  5:59                                 ` Ramuthevar, Vadivel MuruganX [this message]
2020-02-19  2:28   ` [PATCH v10 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-02-19  8:28   ` [PATCH v10 0/2] " Marek Vasut
2020-02-25  4:23   ` Vignesh Raghavendra
     [not found]     ` <99f7e23f-268d-f32b-086f-4a46fc232ce9-l0cyMroinI0@public.gmane.org>
2020-02-25  6:33       ` Ramuthevar, Vadivel MuruganX

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