From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Grant Likely" Subject: Re: [PATCH 3/4] spi: Add OF binding support for SPI busses Date: Sat, 24 May 2008 00:25:47 -0600 Message-ID: References: <20080516193054.28030.35126.stgit@trillian.secretlab.ca> <716a0f1b6c9a544b480c06a329072483@kernel.crashing.org> <200805221926.24112.david-b@pacbell.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: fabrizio.garetto-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, Segher Boessenkool , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linuxppc-dev-mnsaURCQ41sdnm+yROfE0A@public.gmane.org, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, Guennadi Liakhovetski To: "David Brownell" Return-path: In-Reply-To: <200805221926.24112.david-b-yBeKhBN/0LDR7s880joybQ@public.gmane.org> Content-Disposition: inline List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: spi-devel-general-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: spi-devel-general-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: linux-spi.vger.kernel.org On Thu, May 22, 2008 at 8:26 PM, David Brownell wrote: > On Wednesday 21 May 2008, Grant Likely wrote: >> > spi-controller { >> > #address-cells = 2; >> > #size-cells = 0; >> > some-device@0,f000 { reg = < 0 f000 >; } // CS 0, SPI address f000 >> > some-device@1,f000 { reg = < 1 f000 >; } // CS 1, SPI address f000 >> > some-device@1,ff00 { reg = < 1 ff00 >; } // CS 1, SPI address ff00 >> > } >> >> For SPI the CS # *is* the address. :-) >> >> Unlike I2C, SPI doesn't impose any protocol on the data. It is all >> anonymous data out, anonymous data in, a clock and a chip select. > > Very true ... but then there are SPI chips which embed addressing. > > I have in mind the mcp23s08 (and mcp23s17) GPIO expanders, which > support up to four chips wired in parallel on a given chipselect. > The devices are distinguished by how two address pins are wired; > and two bits in the command byte must match them. (I think they > just recycled an I2C design into the SPI world.) Very good point. Okay, so we cannot assume any correlation between the number of CS lines and the number of child nodes to the SPI bus. Cheers, g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/