From: Sergei Shtylyov <sergei.shtylyov@gmail.com>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>,
linux-staging@lists.linux.dev
Cc: gregkh@linuxfoundation.org, neil@brown.name,
linux-mips@vger.kernel.org, tsbogend@alpha.franken.de,
ilya.lipnitskiy@gmail.com, john@phrozen.org
Subject: Re: [PATCH 1/3] MIPS: ralink: Define PCI_IOBASE
Date: Mon, 14 Jun 2021 12:13:29 +0300 [thread overview]
Message-ID: <12f81f6e-41be-7e0f-5590-67591c722a38@gmail.com> (raw)
In-Reply-To: <20210613155623.17233-2-sergio.paracuellos@gmail.com>
Hello!
On 13.06.2021 18:56, Sergio Paracuellos wrote:
> PCI_IOBASE is used to create VM maps for PCI I/O ports, it is
> required by generic PCI drivers to make memory mapped I/O range
> work. Hence define it for ralink architectures to be able to
> avoid parsing manually IO ranges in PCI generic driver code.
> Function 'plat_mem_setup' for ralink is using 'set_io_port_base'
> call using '0xa0000000' as address, so use the same address in
> the definition to align things.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
> arch/mips/include/asm/mach-ralink/spaces.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
> create mode 100644 arch/mips/include/asm/mach-ralink/spaces.h
>
> diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h
> new file mode 100644
> index 000000000000..ec58d4a9ed05
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-ralink/spaces.h
> @@ -0,0 +1,10 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ASM_MACH_RALINK_SPACES_H_
> +#define __ASM_MACH_RALINK_SPACES_H_
> +
> +#define PCI_IOBASE _AC(0xa0000000, UL)
> +#define PCI_IOSIZE SZ_16M
> +#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
Why this sudden switch to spaces for indentation? Previous lines were
(correctly) indented with tabs...
> +
> +#include <asm/mach-generic/spaces.h>
> +#endif
MBR, Sergei
next prev parent reply other threads:[~2021-06-14 9:13 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-13 15:56 [PATCH 0/3] staging: mt7621-pci: define ralink PCI_IOBASE to avoid manually ranges parsing Sergio Paracuellos
2021-06-13 15:56 ` [PATCH 1/3] MIPS: ralink: Define PCI_IOBASE Sergio Paracuellos
2021-06-14 9:13 ` Sergei Shtylyov [this message]
2021-06-14 9:56 ` Sergio Paracuellos
2021-06-13 15:56 ` [PATCH 2/3] staging: mt7621-pci: remove 'mt7621_pci_parse_request_of_pci_ranges' Sergio Paracuellos
2021-06-13 15:56 ` [PATCH 3/3] staging: mt7621-dts: fix pci address for PCI memory range Sergio Paracuellos
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