From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: linux-staging@lists.linux.dev
Cc: gregkh@linuxfoundation.org, neil@brown.name, dan.carpenter@oracle.com
Subject: [PATCH v3 3/6] staging: mt7621-pci: use {readl|writel}_relaxed instead of readl/writel
Date: Mon, 7 Jun 2021 14:01:50 +0200 [thread overview]
Message-ID: <20210607120153.24989-4-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20210607120153.24989-1-sergio.paracuellos@gmail.com>
The driver does not perform DMA, so it's safe to use the relaxed version
for both readl and writel operations.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index b83c338a2e3d..8d14d0f9f769 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -109,32 +109,32 @@ struct mt7621_pcie {
static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
{
- return readl(pcie->base + reg);
+ return readl_relaxed(pcie->base + reg);
}
static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
{
- writel(val, pcie->base + reg);
+ writel_relaxed(val, pcie->base + reg);
}
static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
{
- u32 val = readl(pcie->base + reg);
+ u32 val = readl_relaxed(pcie->base + reg);
val &= ~clr;
val |= set;
- writel(val, pcie->base + reg);
+ writel_relaxed(val, pcie->base + reg);
}
static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
{
- return readl(port->base + reg);
+ return readl_relaxed(port->base + reg);
}
static inline void pcie_port_write(struct mt7621_pcie_port *port,
u32 val, u32 reg)
{
- writel(val, port->base + reg);
+ writel_relaxed(val, port->base + reg);
}
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
@@ -151,7 +151,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where);
- writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
+ writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
}
--
2.25.1
next prev parent reply other threads:[~2021-06-07 12:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 12:01 [PATCH v3 0/6] staging: mt7621-pci: some required changes after first review Sergio Paracuellos
2021-06-07 12:01 ` [PATCH v3 1/6] staging: mt7621-pci: make cleaner 'mt7621_pcie_enable_ports' Sergio Paracuellos
2021-06-07 12:01 ` [PATCH v3 2/6] staging: mt7621-pci: remove 'RALINK_PCI_BAR0SETUP_ADDR' definition Sergio Paracuellos
2021-06-07 12:01 ` Sergio Paracuellos [this message]
2021-06-07 12:01 ` [PATCH v3 4/6] staging: mt7621-dts: move some properties into root port child nodes Sergio Paracuellos
2021-06-07 12:01 ` [PATCH v3 5/6] staging: mt7621-pci: parse some dt properties from " Sergio Paracuellos
2021-06-07 12:01 ` [PATCH v3 6/6] staging: mt7621-pci: make use of 'pcie_port_write' Sergio Paracuellos
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