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[93.71.218.228]) by smtp.gmail.com with ESMTPSA id a4sm1960203edb.79.2021.09.22.14.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Sep 2021 14:50:29 -0700 (PDT) From: Tommaso Merciai To: Cc: tomm.merciai@gmail.com, Forest Bond , Greg Kroah-Hartman , Yujia Qiao , Lucas Henneman , Madhumitha Prabakaran , linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH] staging: vt6655: Replace camel case variables Date: Wed, 22 Sep 2021 23:50:24 +0200 Message-Id: <20210922215026.572424-1-tomm.merciai@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Work in progress: replace camel case variables. Signed-off-by: Tommaso Merciai --- drivers/staging/vt6655/baseband.c | 50 +++++++++++++++---------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c index f73f3fad3e05..93640311f8e3 100644 --- a/drivers/staging/vt6655/baseband.c +++ b/drivers/staging/vt6655/baseband.c @@ -500,7 +500,7 @@ static const unsigned char by_vt3253_init_tab_rfmd[CB_VT3253_INIT_FOR_RFMD][2] = }; #define CB_VT3253B0_INIT_FOR_RFMD 256 -static const unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = { +static const unsigned char by_vt3253b0_rfmd[CB_VT3253B0_INIT_FOR_RFMD][2] = { {0x00, 0x31}, {0x01, 0x00}, {0x02, 0x00}, @@ -762,7 +762,7 @@ static const unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = { #define CB_VT3253B0_AGC_FOR_RFMD2959 195 /* For RFMD2959 */ static -unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = { +unsigned char by_vt3253b0_agc4_rfmd2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = { {0xF0, 0x00}, {0xF1, 0x3E}, {0xF0, 0x80}, @@ -963,7 +963,7 @@ unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = { #define CB_VT3253B0_INIT_FOR_AIROHA2230 256 /* For AIROHA */ static -unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = { +unsigned char by_vt3253b0_airoha2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = { {0x00, 0x31}, {0x01, 0x00}, {0x02, 0x00}, @@ -1224,7 +1224,7 @@ unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = { #define CB_VT3253B0_INIT_FOR_UW2451 256 /* For UW2451 */ -static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = { +static unsigned char by_vt3253b0_uw2451[CB_VT3253B0_INIT_FOR_UW2451][2] = { {0x00, 0x31}, {0x01, 0x00}, {0x02, 0x00}, @@ -1485,7 +1485,7 @@ static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = { #define CB_VT3253B0_AGC 193 /* For AIROHA */ -static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = { +static unsigned char by_vt3253b0_agc[CB_VT3253B0_AGC][2] = { {0xF0, 0x00}, {0xF1, 0x00}, {0xF0, 0x80}, @@ -2006,13 +2006,13 @@ bool bb_vt3253_init(struct vnt_private *priv) } else { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++) result &= bb_write_embedded(priv, - byVT3253B0_RFMD[ii][0], - byVT3253B0_RFMD[ii][1]); + by_vt3253b0_rfmd[ii][0], + by_vt3253b0_rfmd[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AGC4_RFMD2959[ii][0], - byVT3253B0_AGC4_RFMD2959[ii][1]); + by_vt3253b0_agc4_rfmd2959[ii][0], + by_vt3253b0_agc4_rfmd2959[ii][1]); VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23); MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0)); @@ -2028,12 +2028,12 @@ bool bb_vt3253_init(struct vnt_private *priv) } else if ((by_rf_type == RF_AIROHA) || (by_rf_type == RF_AL2230S)) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AIROHA2230[ii][0], - byVT3253B0_AIROHA2230[ii][1]); + by_vt3253b0_airoha2230[ii][0], + by_vt3253b0_airoha2230[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + by_vt3253b0_agc[ii][0], by_vt3253b0_agc[ii][1]); priv->abyBBVGA[0] = 0x1C; priv->abyBBVGA[1] = 0x10; @@ -2046,13 +2046,13 @@ bool bb_vt3253_init(struct vnt_private *priv) } else if (by_rf_type == RF_UW2451) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) result &= bb_write_embedded(priv, - byVT3253B0_UW2451[ii][0], - byVT3253B0_UW2451[ii][1]); + by_vt3253b0_uw2451[ii][0], + by_vt3253b0_uw2451[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AGC[ii][0], - byVT3253B0_AGC[ii][1]); + by_vt3253b0_agc[ii][0], + by_vt3253b0_agc[ii][1]); VNSvOutPortB(iobase + MAC_REG_ITRTMSET, 0x23); MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0)); @@ -2068,8 +2068,8 @@ bool bb_vt3253_init(struct vnt_private *priv) } else if (by_rf_type == RF_UW2452) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) result &= bb_write_embedded(priv, - byVT3253B0_UW2451[ii][0], - byVT3253B0_UW2451[ii][1]); + by_vt3253b0_uw2451[ii][0], + by_vt3253b0_uw2451[ii][1]); /* Init ANT B select, * TX Config CR09 = 0x61->0x45, @@ -2101,7 +2101,7 @@ bool bb_vt3253_init(struct vnt_private *priv) for (ii = 0; ii < CB_VT3253B0_AGC; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + by_vt3253b0_agc[ii][0], by_vt3253b0_agc[ii][1]); priv->abyBBVGA[0] = 0x14; priv->abyBBVGA[1] = 0x0A; @@ -2116,12 +2116,12 @@ bool bb_vt3253_init(struct vnt_private *priv) } else if (by_rf_type == RF_VT3226) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AIROHA2230[ii][0], - byVT3253B0_AIROHA2230[ii][1]); + by_vt3253b0_airoha2230[ii][0], + by_vt3253b0_airoha2230[ii][1]); for (ii = 0; ii < CB_VT3253B0_AGC; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + by_vt3253b0_agc[ii][0], by_vt3253b0_agc[ii][1]); priv->abyBBVGA[0] = 0x1C; priv->abyBBVGA[1] = 0x10; @@ -2137,8 +2137,8 @@ bool bb_vt3253_init(struct vnt_private *priv) } else if (by_rf_type == RF_AIROHA7230) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AIROHA2230[ii][0], - byVT3253B0_AIROHA2230[ii][1]); + by_vt3253b0_airoha2230[ii][0], + by_vt3253b0_airoha2230[ii][1]); /* {{ RobertYu:20050223, request by JerryChung */ /* Init ANT B select,TX Config CR09 = 0x61->0x45, @@ -2155,7 +2155,7 @@ bool bb_vt3253_init(struct vnt_private *priv) for (ii = 0; ii < CB_VT3253B0_AGC; ii++) result &= bb_write_embedded(priv, - byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + by_vt3253b0_agc[ii][0], by_vt3253b0_agc[ii][1]); priv->abyBBVGA[0] = 0x1C; priv->abyBBVGA[1] = 0x10; -- 2.25.1