From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4ABF7E for ; Tue, 26 Apr 2022 13:50:44 +0000 (UTC) Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:8ccc:428d:6d90:c434]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id D48CF1F43AFF; Tue, 26 Apr 2022 14:50:42 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1650981043; bh=CCDHj7pQZvESZdZWN4cCNttODXVw+AkYBsGRVPKNBSI=; h=From:To:Cc:Subject:Date:From; b=g5sJ06ErarEfsR+65HFsTR/u0T8G7iZ8X0qaQ8rwAjfugnHDiQPv3OGLnQ89gF1Uw Z/FZL4XZvK+vlQW2B+VBHyaq3nn6SvPofdyGl8W9P7xGDJXAUDSzf/SbeIy02IX0KE XGJpgaulJImaaLHQwnHXMFs6CFOT63MlzvVbiS/q1Rb8v0uukUuL/QE839madZ+k3X eS3B0Rfy3vAX4Y84P6vAL8rByNpZeg+tj8m2gTk3dBzJ0QzY4avPpHAKHWmp3vEltm aniSFOqb/zvsOOmY/50QjHRIDX2o2O5Dw5Z+4ikidntoTcBriOEJK3YWGiEMiZVaYk RhPvk0FcLViRg== From: Benjamin Gaignard To: ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, mchehab@kernel.org, gregkh@linuxfoundation.org Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, jon@nanocrew.net, aford173@gmail.com, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v2] media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values Date: Tue, 26 Apr 2022 15:50:34 +0200 Message-Id: <20220426135034.694655-1-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.32.0 Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT flag value. This fix CAINIT_G_SHARP_3 test in fluster. Signed-off-by: Benjamin Gaignard --- drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c index 6deb31b7b993..503f4b028bc5 100644 --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); } - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); - } else { - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); - } + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); -- 2.32.0