From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C6712F82 for ; Thu, 29 Apr 2021 21:34:32 +0000 (UTC) Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lcEAg-001iK5-7t; Thu, 29 Apr 2021 23:26:06 +0200 Date: Thu, 29 Apr 2021 23:26:06 +0200 From: Andrew Lunn To: DENG Qingfang Cc: "David S. Miller" , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org, Weijie Gao , Chuanhong Guo , =?iso-8859-1?Q?Ren=E9?= van Dorst , Frank Wunderlich , Thomas Gleixner , Marc Zyngier Subject: Re: [PATCH net-next 1/4] net: phy: add MediaTek PHY driver Message-ID: References: <20210429062130.29403-1-dqfext@gmail.com> <20210429062130.29403-2-dqfext@gmail.com> X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210429062130.29403-2-dqfext@gmail.com> On Thu, Apr 29, 2021 at 02:21:27PM +0800, DENG Qingfang wrote: > Add support for MediaTek PHYs found in MT7530 and MT7531 switches. > The initialization procedure is from the vendor driver, but due to lack > of documentation, the function of some register values remains unknown. > > Signed-off-by: DENG Qingfang Reviewed-by: Andrew Lunn > + > + /* Enable HW auto downshift */ > + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); As a follow up patch, you could add support for controlling this via a PHY tunable. Andrew