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Date: Fri, 14 May 2021 16:16:54 +0530
From: Vinod Koul <vkoul@kernel.org>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: kishon@ti.com, devicetree@vger.kernel.org,
	linux-phy@lists.infradead.org, robh+dt@kernel.org,
	linux-staging@lists.linux.dev, gregkh@linuxfoundation.org,
	neil@brown.name, ilya.lipnitskiy@gmail.com
Subject: Re: [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some
 improvements
Message-ID: <YJ5VHnZaLi4o31vL@vkoul-mobl.Dlink>
References: <20210508070930.5290-1-sergio.paracuellos@gmail.com>
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In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com>

On 08-05-21, 09:09, Sergio Paracuellos wrote:
> Hi all,
> 
> This series contains some improvements in the pci phy driver
> for MT7621 SoCs.
> 
> MT7621 SoC clock driver has already mainlined in
> 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
> 
> Because of this we can update schema documentation and device tree
> to add related clock entries and avoid custom architecture code
> in favour of using the clock kernel framework to retrieve clock
> frequency needed to properly configure the PCIe related Phys.
> 
> After this changes there is no problem to properly enable this
> driver for COMPILE_TEST.
> 
> Configuration has also modified from 'tristate' to 'bool' depending
> on PCI_MT7621 which seems to have more sense.

Applied 2-6, thanks

-- 
~Vinod