[PATCH v2 0/5] arm64: sunxi: Enable the sun4i timer

[PATCH v2 0/5] arm64: sunxi: Enable the sun4i timer

[Samuel Holland]

In preparation for adding CPU idle states, hook up the sun4i timer.
Having a non-c3stop clockevent source available is necessary for all
CPUs to simultaneously enter a local-timer-stop idle state.

Changes from v1:
  - Removed H616 changes (depends on an unmerged patch set)
  - Reworded the patch 4-5 commit messages for clarity
  - Added Acked-by tags

Samuel Holland (5):
  dt-bindings: timer: Simplify conditional expressions
  dt-bindings: timer: Add compatibles for sun50i timers
  arm64: dts: allwinner: a64: Sort watchdog node
  arm64: dts: allwinner: Add sun4i MMIO timer nodes
  arm64: sunxi: Build the sun4i timer driver

 .../timer/allwinner,sun4i-a10-timer.yaml      | 42 +++++++++----------
 arch/arm64/Kconfig.platforms                  |  1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++----
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  9 ++++
 4 files changed, 46 insertions(+), 31 deletions(-)

-- 
2.26.2

[PATCH v2 1/5] dt-bindings: timer: Simplify conditional expressions

[Samuel Holland]

The sun4i timer IP block has a variable number of interrupts based on
the compatible. Use enums to combine the two sections for the existing
3-interrupt variants, and to simplify adding new compatible strings.

Acked-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 .../timer/allwinner,sun4i-a10-timer.yaml      | 25 ++++++-------------
 1 file changed, 7 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 1c7cf32e7ac2..3462598e609d 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -34,8 +34,8 @@ allOf:
   - if:
       properties:
         compatible:
-          items:
-            const: allwinner,sun4i-a10-timer
+          enum:
+            - allwinner,sun4i-a10-timer
 
     then:
       properties:
@@ -46,8 +46,8 @@ allOf:
   - if:
       properties:
         compatible:
-          items:
-            const: allwinner,sun8i-a23-timer
+          enum:
+            - allwinner,sun8i-a23-timer
 
     then:
       properties:
@@ -58,20 +58,9 @@ allOf:
   - if:
       properties:
         compatible:
-          items:
-            const: allwinner,sun8i-v3s-timer
-
-    then:
-      properties:
-        interrupts:
-          minItems: 3
-          maxItems: 3
-
-  - if:
-      properties:
-        compatible:
-          items:
-            const: allwinner,suniv-f1c100s-timer
+          enum:
+            - allwinner,sun8i-v3s-timer
+            - allwinner,suniv-f1c100s-timer
 
     then:
       properties:
-- 
2.26.2

[PATCH v2 2/5] dt-bindings: timer: Add compatibles for sun50i timers

[Samuel Holland]

The sun50i SoCs contain timer blocks which are useful as broadcast
clockevent sources. They each have 2 interrupts, matching the A23
variant, so add the new compatible strings with the A23 compatible
as a fallback.

Acked-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 .../timer/allwinner,sun4i-a10-timer.yaml        | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 3462598e609d..53fd24bdc34e 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -12,11 +12,18 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - allwinner,sun4i-a10-timer
-      - allwinner,sun8i-a23-timer
-      - allwinner,sun8i-v3s-timer
-      - allwinner,suniv-f1c100s-timer
+    oneOf:
+      - enum:
+          - allwinner,sun4i-a10-timer
+          - allwinner,sun8i-a23-timer
+          - allwinner,sun8i-v3s-timer
+          - allwinner,suniv-f1c100s-timer
+      - items:
+          - enum:
+              - allwinner,sun50i-a64-timer
+              - allwinner,sun50i-h6-timer
+              - allwinner,sun50i-h616-timer
+          - const: allwinner,sun8i-a23-timer
 
   reg:
     maxItems: 1
-- 
2.26.2

[PATCH v2 3/5] arm64: dts: allwinner: a64: Sort watchdog node

[Samuel Holland]

Nodes should be sorted by unit address. Move the watchdog node to the
correct place, so it will be next to the timer node when that is added.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 57786fc120c3..9cac88576975 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -798,6 +798,14 @@ uart4_rts_cts_pins: uart4-rts-cts-pins {
 			};
 		};
 
+		wdt0: watchdog@1c20ca0 {
+			compatible = "allwinner,sun50i-a64-wdt",
+				     "allwinner,sun6i-a31-wdt";
+			reg = <0x01c20ca0 0x20>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		spdif: spdif@1c21000 {
 			#sound-dai-cells = <0>;
 			compatible = "allwinner,sun50i-a64-spdif",
@@ -1321,13 +1329,5 @@ r_rsb: rsb@1f03400 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
-
-		wdt0: watchdog@1c20ca0 {
-			compatible = "allwinner,sun50i-a64-wdt",
-				     "allwinner,sun6i-a31-wdt";
-			reg = <0x01c20ca0 0x20>;
-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc24M>;
-		};
 	};
 };
-- 
2.26.2

[PATCH v2 4/5] arm64: dts: allwinner: Add sun4i MMIO timer nodes

[Samuel Holland]

For a CPU to enter an idle state, some timer must be available to
trigger an IRQ and wake it back up. The local ARM architectural timer is
not sufficient, because that timer stops when the CPU is powered down.
The ARM architectural timer from some other CPU can be used, but doing
so prevents that other CPU from entering an idle state. For all CPUs to
power down at the same time, Linux needs a timer which is not tied to
any CPU.

Hook up the "sun4i" timer so it can be used for this purpose. It runs at
24 MHz, which balances resolution and power consumption.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 9 +++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 9cac88576975..c89032dfb316 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -798,6 +798,15 @@ uart4_rts_cts_pins: uart4-rts-cts-pins {
 			};
 		};
 
+		timer@1c20c00 {
+			compatible = "allwinner,sun50i-a64-timer",
+				     "allwinner,sun8i-a23-timer";
+			reg = <0x01c20c00 0xa0>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		wdt0: watchdog@1c20ca0 {
 			compatible = "allwinner,sun50i-a64-wdt",
 				     "allwinner,sun6i-a31-wdt";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 49e979794094..01884b32390d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -271,6 +271,15 @@ cpu_speed_grade: cpu-speed-grade@1c {
 			};
 		};
 
+		timer@3009000 {
+			compatible = "allwinner,sun50i-h6-timer",
+				     "allwinner,sun8i-a23-timer";
+			reg = <0x03009000 0xa0>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		watchdog: watchdog@30090a0 {
 			compatible = "allwinner,sun50i-h6-wdt",
 				     "allwinner,sun6i-a31-wdt";
-- 
2.26.2

[PATCH v2 5/5] arm64: sunxi: Build the sun4i timer driver

[Samuel Holland]

While the ARM architectural timer is generatlly the best timer to use,
a non-c3stop timer is needed for cpuidle.

Build the "sun4i" timer driver so it can be used for this purpose.
It is present on all 64-bit sunxi SoCs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm64/Kconfig.platforms | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index cdfd5fed457f..7f6a66431fa7 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -26,6 +26,7 @@ config ARCH_SUNXI
 	select IRQ_FASTEOI_HIERARCHY_HANDLERS
 	select PINCTRL
 	select RESET_CONTROLLER
+	select SUN4I_TIMER
 	help
 	  This enables support for Allwinner sunxi based SoCs like the A64.
 
-- 
2.26.2

Re: [PATCH v2 0/5] arm64: sunxi: Enable the sun4i timer

[Daniel Lezcano]

On 22/03/2021 05:47, Samuel Holland wrote:
> In preparation for adding CPU idle states, hook up the sun4i timer.
> Having a non-c3stop clockevent source available is necessary for all
> CPUs to simultaneously enter a local-timer-stop idle state.

Why simultaneously ?

> Changes from v1:
>   - Removed H616 changes (depends on an unmerged patch set)
>   - Reworded the patch 4-5 commit messages for clarity
>   - Added Acked-by tags
> 
> Samuel Holland (5):
>   dt-bindings: timer: Simplify conditional expressions
>   dt-bindings: timer: Add compatibles for sun50i timers
>   arm64: dts: allwinner: a64: Sort watchdog node
>   arm64: dts: allwinner: Add sun4i MMIO timer nodes
>   arm64: sunxi: Build the sun4i timer driver
> 
>  .../timer/allwinner,sun4i-a10-timer.yaml      | 42 +++++++++----------
>  arch/arm64/Kconfig.platforms                  |  1 +
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++----
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  9 ++++
>  4 files changed, 46 insertions(+), 31 deletions(-)
> 


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Re: [PATCH v2 0/5] arm64: sunxi: Enable the sun4i timer

[Samuel Holland]

On 3/22/21 9:18 AM, Daniel Lezcano wrote:
> On 22/03/2021 05:47, Samuel Holland wrote:
>> In preparation for adding CPU idle states, hook up the sun4i timer.
>> Having a non-c3stop clockevent source available is necessary for all
>> CPUs to simultaneously enter a local-timer-stop idle state.
> 
> Why simultaneously ?
Because the CPU providing (the hrtimer providing) the broadcast timer
cannot enter an idle state which would stop that timer. So in my case,
with 4 CPUs, I was seeing at most 3 CPUs enter idle at any given time.
This prevented any cluster-level idle states from doing anything. After
applying this series, I was able to observe the whole cluster powering
down when appropriate.

Regards,
Samuel

>> Changes from v1:
>>   - Removed H616 changes (depends on an unmerged patch set)
>>   - Reworded the patch 4-5 commit messages for clarity
>>   - Added Acked-by tags
>>
>> Samuel Holland (5):
>>   dt-bindings: timer: Simplify conditional expressions
>>   dt-bindings: timer: Add compatibles for sun50i timers
>>   arm64: dts: allwinner: a64: Sort watchdog node
>>   arm64: dts: allwinner: Add sun4i MMIO timer nodes
>>   arm64: sunxi: Build the sun4i timer driver
>>
>>  .../timer/allwinner,sun4i-a10-timer.yaml      | 42 +++++++++----------
>>  arch/arm64/Kconfig.platforms                  |  1 +
>>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++----
>>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  9 ++++
>>  4 files changed, 46 insertions(+), 31 deletions(-)
>>
> 
> 

Re: [PATCH v2 0/5] arm64: sunxi: Enable the sun4i timer

[Daniel Lezcano]

On 24/03/2021 04:51, Samuel Holland wrote:
> On 3/22/21 9:18 AM, Daniel Lezcano wrote:
>> On 22/03/2021 05:47, Samuel Holland wrote:
>>> In preparation for adding CPU idle states, hook up the sun4i timer.
>>> Having a non-c3stop clockevent source available is necessary for all
>>> CPUs to simultaneously enter a local-timer-stop idle state.
>>
>> Why simultaneously ?
> Because the CPU providing (the hrtimer providing) the broadcast timer
> cannot enter an idle state which would stop that timer. So in my case,
> with 4 CPUs, I was seeing at most 3 CPUs enter idle at any given time.
> This prevented any cluster-level idle states from doing anything. After
> applying this series, I was able to observe the whole cluster powering
> down when appropriate.

Ah, ok. I did not realize this fourth CPU was acting as the broadcast
timer, so allowing at least a CPU power down. This setup is unusual.

The changes make sense.

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>



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Re: [PATCH v2 1/5] dt-bindings: timer: Simplify conditional expressions

[Rob Herring]

On Sun, 21 Mar 2021 23:47:03 -0500, Samuel Holland wrote:
> The sun4i timer IP block has a variable number of interrupts based on
> the compatible. Use enums to combine the two sections for the existing
> 3-interrupt variants, and to simplify adding new compatible strings.
> 
> Acked-by: Maxime Ripard <maxime@cerno.tech>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>  .../timer/allwinner,sun4i-a10-timer.yaml      | 25 ++++++-------------
>  1 file changed, 7 insertions(+), 18 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 2/5] dt-bindings: timer: Add compatibles for sun50i timers

[Rob Herring]

On Sun, 21 Mar 2021 23:47:04 -0500, Samuel Holland wrote:
> The sun50i SoCs contain timer blocks which are useful as broadcast
> clockevent sources. They each have 2 interrupts, matching the A23
> variant, so add the new compatible strings with the A23 compatible
> as a fallback.
> 
> Acked-by: Maxime Ripard <maxime@cerno.tech>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>  .../timer/allwinner,sun4i-a10-timer.yaml        | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>