From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 45FC02F80 for ; Mon, 24 May 2021 12:33:18 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 49E77113E; Mon, 24 May 2021 05:33:17 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B72CD3F719; Mon, 24 May 2021 05:33:15 -0700 (PDT) Date: Mon, 24 May 2021 13:33:01 +0100 From: Andre Przywara To: Ralf Schlatterbeck Cc: Mark Brown , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Mirko Vogt Subject: Re: [PATCH 1/1] spi-sun6i: Fix chipselect/clock bug Message-ID: <20210524133301.32c74794@slackpad.fritz.box> In-Reply-To: <20210521201913.2gapcmrzynxekro7@runtux.com> References: <20210520100656.rgkdexdvrddt3upy@runtux.com> <20210521173011.1c602682@slackpad.fritz.box> <20210521201913.2gapcmrzynxekro7@runtux.com> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 21 May 2021 22:19:13 +0200 Ralf Schlatterbeck wrote: Hi, > From: Mirko Vogt > > The current sun6i SPI implementation initializes the transfer too early, > resulting in SCK going high before the transfer. When using an additional > (gpio) chipselect with sun6i, the chipselect is asserted at a time when > clock is high, making the SPI transfer fail. > > This is due to SUN6I_GBL_CTL_BUS_ENABLE being written into > SUN6I_GBL_CTL_REG at an early stage. Moving that to the transfer > function, hence, right before the transfer starts, mitigates that > problem. > > Signed-off-by: Mirko Vogt > Signed-off-by: Ralf Schlatterbeck Looks good to me now, thanks for the changes! Reviewed-by: Andre Przywara Some comments for future contributions (should not hold back that patch, I think): - Single patch set series don't bother to have a "1/1" after the "PATCH". - You are expected to increase the version number when you send a new version, to show that *this* is better than the previous post and this version should be merged. Otherwise the maintainer might pick the wrong version. "git format-patch -v2" and "git send-email" will automatically take care of this. > --- > Updated patch with suggested improvements by Andre Przywara > For oscilloscope screenshots with/without the patch, see my blog post > https://blog.runtux.com/posts/2019/04/18/ > or the discussion in the armbian forum at > https://forum.armbian.com/topic/4330-spi-gpio-chip-select-support/ > (my logo there is a penguin). Please keep in mind that text after the dashes doesn't make it in it repo, so this information would be lost there. Also, in general links in commit messages are somewhat frowned upon, since they tend to 404 sooner or later. So ideally you can put a condensed version of your findings into the commit message? Don't worry if it grows long, it is not uncommon to have a 2 page commit message for a one-liner patch. Cheers, Andre > > drivers/spi/spi-sun6i.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c > index cc8401980125..23ad052528db 100644 > --- a/drivers/spi/spi-sun6i.c > +++ b/drivers/spi/spi-sun6i.c > @@ -379,6 +379,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master, > } > > sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); > + /* Finally enable the bus - doing so before might raise SCK to HIGH */ > + reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); > + reg |= SUN6I_GBL_CTL_BUS_ENABLE; > + sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); > > /* Setup the transfer now... */ > if (sspi->tx_buf) > @@ -504,7 +508,7 @@ static int sun6i_spi_runtime_resume(struct device *dev) > } > > sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, > - SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); > + SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); > > return 0; >