From: Andre Przywara <andre.przywara@arm.com>
To: Jagan Teki <jagan@amarulasolutions.com>, Peng Fan <peng.fan@nxp.com>
Cc: u-boot@lists.denx.de, Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Ondrej Jirman <megous@megous.com>,
linux-sunxi@lists.linux.dev
Subject: [PATCH 4/8] mmc: sunxi: Cleanup "new timing mode" selection
Date: Tue, 25 May 2021 00:30:25 +0100 [thread overview]
Message-ID: <20210524233029.16417-5-andre.przywara@arm.com> (raw)
In-Reply-To: <20210524233029.16417-1-andre.przywara@arm.com>
Among the SoCs using the "new timing mode", only the A83T needs to
explicitly switch to that mode.
By just defining the symbol for that one odd A83T bit to 0 for any other
SoCs, we can always OR that in, and save the confusing nested #ifdefs.
Clean up the also confusing new_mode setting on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/mmc/sunxi_mmc.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index bc68debdad6..33cedb4edba 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -23,6 +23,10 @@
#include <asm-generic/gpio.h>
#include <linux/delay.h>
+#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
+#define CCM_MMC_CTRL_MODE_SEL_NEW 0
+#endif
+
struct sunxi_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -102,13 +106,10 @@ static int mmc_resource_init(int sdc_no)
static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
{
unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
- bool new_mode = true;
+ bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
bool calibrate = false;
u32 val = 0;
- if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
- new_mode = false;
-
/* A83T support new mode only on eMMC */
if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
new_mode = false;
@@ -176,12 +177,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
}
if (new_mode) {
-#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
-#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
- val = CCM_MMC_CTRL_MODE_SEL_NEW;
-#endif
+ val |= CCM_MMC_CTRL_MODE_SEL_NEW;
setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
-#endif
} else if (!calibrate) {
/*
* Use hardcoded delay values if controller doesn't support
--
2.17.5
next prev parent reply other threads:[~2021-05-24 23:30 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-24 23:30 [PATCH 0/8] sunxi: mmc: Fixes and speed increase Andre Przywara
2021-05-24 23:30 ` [PATCH 1/8] mmc: sunxi: Avoid #ifdefs in delay and width setup Andre Przywara
2021-05-25 1:42 ` Jaehoon Chung
2021-05-24 23:30 ` [PATCH 2/8] mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT Andre Przywara
2021-05-25 1:43 ` Jaehoon Chung
2021-05-24 23:30 ` [PATCH 3/8] mmc: sunxi: Fix MMC clock parent selection Andre Przywara
2021-05-24 23:30 ` Andre Przywara [this message]
2021-05-25 1:43 ` [PATCH 4/8] mmc: sunxi: Cleanup "new timing mode" selection Jaehoon Chung
2021-05-24 23:30 ` [PATCH 5/8] mmc: sunxi: Enable "new timing mode" on all new SoCs Andre Przywara
2021-05-24 23:30 ` [PATCH 6/8] mmc: sunxi: Cleanup and fix self-calibration code Andre Przywara
2021-05-24 23:30 ` [PATCH 7/8] mmc: sunxi: Increase MMIO FIFO read performance Andre Przywara
2021-05-24 23:30 ` [PATCH 8/8] mmc: sunxi: Use mmc_of_parse() Andre Przywara
2021-05-25 1:43 ` Jaehoon Chung
2021-07-03 23:24 ` [PATCH 0/8] sunxi: mmc: Fixes and speed increase Andre Przywara
2021-07-04 19:56 ` Samuel Holland
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