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[89.103.215.157]) by smtp.gmail.com with ESMTPSA id h9sm6238376edt.18.2021.05.30.21.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 May 2021 21:46:20 -0700 (PDT) From: Roman Beranek X-Google-Original-From: Roman Beranek To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Thierry Reding , Emil Lenngren , Pascal Roeleven , Lee Jones , Maxime Ripard , Chen-Yu Tsai , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com Subject: [PATCH 3/6] pwm: sun4i: replace spinlock with a mutex Date: Mon, 31 May 2021 06:46:05 +0200 Message-Id: <20210531044608.1006024-4-roman.beranek@prusa3d.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210531044608.1006024-1-roman.beranek@prusa3d.com> References: <20210531044608.1006024-1-roman.beranek@prusa3d.com> X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Releasing ctrl_lock for the duration of the delay is not desirable as it allows re-enabling the PWM before the delay is over. Instead, substitute the spinlock with a mutex so that we can sleep while holding it. Signed-off-by: Roman Beranek --- drivers/pwm/pwm-sun4i.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 2777abe66f79..b3ec59a83d00 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -16,13 +16,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #define PWM_CTRL_REG 0x0 @@ -87,7 +87,7 @@ struct sun4i_pwm_chip { struct clk *clk; struct reset_control *rst; void __iomem *base; - spinlock_t ctrl_lock; + struct mutex ctrl_lock; const struct sun4i_pwm_data *data; unsigned long next_period[2]; }; @@ -265,7 +265,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return ret; } - spin_lock(&sun4i_pwm->ctrl_lock); + mutex_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); if (sun4i_pwm->data->has_direct_mod_clk_output) { @@ -273,7 +273,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); /* We can skip other parameter */ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - spin_unlock(&sun4i_pwm->ctrl_lock); + mutex_unlock(&sun4i_pwm->ctrl_lock); return 0; } @@ -308,10 +308,10 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - spin_unlock(&sun4i_pwm->ctrl_lock); - - if (state->enabled) + if (state->enabled) { + mutex_unlock(&sun4i_pwm->ctrl_lock); return 0; + } /* We need a full period to elapse before disabling the channel. */ now = jiffies; @@ -324,11 +324,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, usleep_range(delay_us, delay_us * 2); } - spin_lock(&sun4i_pwm->ctrl_lock); - ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - spin_unlock(&sun4i_pwm->ctrl_lock); + mutex_unlock(&sun4i_pwm->ctrl_lock); clk_disable_unprepare(sun4i_pwm->clk); @@ -471,7 +469,7 @@ static int sun4i_pwm_probe(struct platform_device *pdev) pwm->chip.of_xlate = of_pwm_xlate_with_flags; pwm->chip.of_pwm_n_cells = 3; - spin_lock_init(&pwm->ctrl_lock); + mutex_init(&pwm->ctrl_lock); ret = pwmchip_add(&pwm->chip); if (ret < 0) { -- 2.31.1