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From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: Roman Beranek <roman.beranek@prusa3d.cz>
Cc: Thierry Reding <thierry.reding@gmail.com>,
	Emil Lenngren <emil.lenngren@gmail.com>,
	Pascal Roeleven <dev@pascalroeleven.nl>,
	Lee Jones <lee.jones@linaro.org>,
	Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com
Subject: Re: [PATCH 2/6] pwm: sun4i: disable EN bit prior to the delay
Date: Mon, 7 Jun 2021 10:07:21 +0200	[thread overview]
Message-ID: <20210607080721.4o2dd4pmb4wwddgg@pengutronix.de> (raw)
In-Reply-To: <20210531044608.1006024-3-roman.beranek@prusa3d.com>

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On Mon, May 31, 2021 at 06:46:04AM +0200, Roman Beranek wrote:
> The reason why we wait before gating the clock is to allow for the PWM
> to finish its cycle and stop. But it won't stop unless the EN bit is
> disabled.
> 
> Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
> ---
>  drivers/pwm/pwm-sun4i.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index 3721b9894cf6..2777abe66f79 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -303,6 +303,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>  
>  	if (state->enabled)
>  		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
> +	else
> +		ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);

Catching the case !state->enabled even earlier would make sense.
Otherwise you might see a needless glitch after

	pwm_apply_state(mypwm, { .period = A, .duty_cycle = B, .enabled = true });
	pwm_apply_state(mypwm, { .period = C, .duty_cycle = D, .enabled = false });

which might make C+D visible on the PWM before disabling.

>  
>  	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
>  
> @@ -325,7 +327,6 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>  	spin_lock(&sun4i_pwm->ctrl_lock);
>  	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>  	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
> -	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
>  	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
>  	spin_unlock(&sun4i_pwm->ctrl_lock);

So the comment

  /* We need a full period to elapse before disabling the channel. */

is wrong?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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  reply	other threads:[~2021-06-07  8:07 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-31  4:46 [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling Roman Beranek
2021-05-31  4:46 ` [PATCH 1/6] pwm: sun4i: enable clk prior to getting its rate Roman Beranek
2021-06-07  8:00   ` Uwe Kleine-König
2021-05-31  4:46 ` [PATCH 2/6] pwm: sun4i: disable EN bit prior to the delay Roman Beranek
2021-06-07  8:07   ` Uwe Kleine-König [this message]
2021-05-31  4:46 ` [PATCH 3/6] pwm: sun4i: replace spinlock with a mutex Roman Beranek
2021-05-31  4:46 ` [PATCH 4/6] pwm: sun4i: simplify calculation of the delay time Roman Beranek
2021-05-31  4:46 ` [PATCH 5/6] pwm: sun4i: shorten the delay to 2 cycles Roman Beranek
2021-05-31  4:46 ` [PATCH 6/6] pwm: sun4i: don't delay if the PWM is already off Roman Beranek
2021-06-10 13:41   ` Pascal Roeleven
2021-05-31 19:07 ` [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling Pascal Roeleven
2021-05-31 20:01   ` Emil Lenngren
2021-05-31 20:20     ` Pascal Roeleven
2021-06-08 12:28   ` Pascal Roeleven

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