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Mon, 7 Jun 2021 08:12:18 -0400 (EDT) Date: Mon, 7 Jun 2021 14:12:16 +0200 From: Maxime Ripard To: Guo Ren Cc: Anup Patel , Palmer Dabbelt , Arnd Bergmann , Chen-Yu Tsai , Drew Fustini , liush@allwinnertech.com, Wei Wu =?utf-8?B?KOWQtOS8nyk=?= , wefu@redhat.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Atish Patra , Christoph Hellwig Subject: Re: [RFC PATCH v2 10/11] riscv: soc: Add Allwinner SoC kconfig option Message-ID: <20210607121216.ypoehirsdypul3br@gilmour> References: <1622970249-50770-1-git-send-email-guoren@kernel.org> <1622970249-50770-14-git-send-email-guoren@kernel.org> <20210607071916.kwdbtafbqp3icgia@gilmour> X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="secwxumdfbdnmyjv" Content-Disposition: inline In-Reply-To: --secwxumdfbdnmyjv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jun 07, 2021 at 03:43:03PM +0800, Guo Ren wrote: > On Mon, Jun 7, 2021 at 3:19 PM Maxime Ripard wrote: > > > > Hi, > > > > On Sun, Jun 06, 2021 at 09:04:08AM +0000, guoren@kernel.org wrote: > > > From: Guo Ren > > > > > > Add Allwinner kconfig option which selects SoC specific and common > > > drivers that is required for this SoC. > > > > > > Allwinner D1 uses custom PTE attributes to solve non-coherency SOC > > > interconnect issues for dma synchronization, so we set the default > > > value when SOC_SUNXI selected. > > > > > > Signed-off-by: Guo Ren > > > Co-Developed-by: Liu Shaohua > > > Signed-off-by: Liu Shaohua > > > Cc: Anup Patel > > > Cc: Atish Patra > > > Cc: Christoph Hellwig > > > Cc: Chen-Yu Tsai > > > Cc: Drew Fustini > > > Cc: Maxime Ripard > > > Cc: Palmer Dabbelt > > > Cc: Wei Fu > > > Cc: Wei Wu > > > --- > > > arch/riscv/Kconfig.socs | 12 ++++++++++++ > > > arch/riscv/configs/defconfig | 1 + > > > 2 files changed, 13 insertions(+) > > > > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > > index ed96376..055fb3e 100644 > > > --- a/arch/riscv/Kconfig.socs > > > +++ b/arch/riscv/Kconfig.socs > > > @@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE > > > > > > endif > > > > > > +config SOC_SUNXI > > > + bool "Allwinner SoCs" > > > + depends on MMU > > > + select DWMAC_GENERIC > > > + select SERIAL_8250 > > > + select SERIAL_8250_CONSOLE > > > + select SERIAL_8250_DW > > > + select SIFIVE_PLIC > > > + select STMMAC_ETH > > > + help > > > + This enables support for Allwinner SoC platforms like the D1. > > > + > > > > We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, > > looks good otherwise. > > > > Maxime > Remove DWMAC, STMMAC_ETH is okay. >=20 > But I think we still need: > select SERIAL_8250_DW if SERIAL_8250 Well, even the UART is optional. Just enable them in the defconfig Maxime --secwxumdfbdnmyjv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYL4NIAAKCRDj7w1vZxhR xXytAP4mGdQrlps0ZkdQRDvgGoPmv63wCOgw7ukUbY9jEwIJGAEAwSHuyXFN1JP5 4ZeSdV0JY7fJXuRP01GiYXItu7FXhg8= =/iVS -----END PGP SIGNATURE----- --secwxumdfbdnmyjv--