From: Maxime Ripard <email@example.com> To: Andre Przywara <firstname.lastname@example.org> Cc: Chen-Yu Tsai <email@example.com>, Jernej Skrabec <firstname.lastname@example.org>, Rob Herring <email@example.com>, Icenowy Zheng <firstname.lastname@example.org>, Samuel Holland <email@example.com>, Ondrej Jirman <firstname.lastname@example.org>, email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, Kishon Vijay Abraham I <email@example.com>, Vinod Koul <firstname.lastname@example.org>, email@example.com, firstname.lastname@example.org Subject: Re: [PATCH v6 12/17] phy: sun4i-usb: Introduce port2 SIDDQ quirk Date: Mon, 7 Jun 2021 15:22:55 +0200 [thread overview] Message-ID: <20210607132255.7fa75a7k7ud2g7ux@gilmour> (raw) In-Reply-To: <email@example.com> [-- Attachment #1: Type: text/plain, Size: 2862 bytes --] Hi, On Tue, May 25, 2021 at 12:29:01PM +0100, Andre Przywara wrote: > On Mon, 24 May 2021 13:59:46 +0200 > Maxime Ripard <firstname.lastname@example.org> wrote: > > Hi Maxime, > > > On Wed, May 19, 2021 at 11:41:47AM +0100, Andre Przywara wrote: > > > At least the Allwinner H616 SoC requires a weird quirk to make most > > > USB PHYs work: Only port2 works out of the box, but all other ports > > > need some help from this port2 to work correctly: The CLK_BUS_PHY2 and > > > RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in > > > the PMU PHY control register needs to be cleared. For this register to > > > be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... > > > > > > Instead of disguising this as some generic feature, do exactly that > > > in our PHY init: > > > If the quirk bit is set, and we initialise a PHY other than PHY2, ungate > > > this one special clock, and clear the SIDDQ bit. We can pull in the > > > other required clocks via the DT. > > > > > > Signed-off-by: Andre Przywara <email@example.com> > > > > What is this SIDDQ bit doing exactly? > > I probably know as much as you do, but as Jernej pointed out, in some > Rockchip code it's indeed documented as some analogue PHY supply switch: > ($ git grep -i siddq drivers/phy/rockchip) > > In fact we had this pin/bit for ages, it was just hidden as BIT(1) in > our infamous PMU_UNK1 register. Patch 10/17 drags that into the light. Ok > > I guess we could also expose this using a power-domain if it's relevant? > > Mmmh, interesting idea. So are you thinking about registering a genpd > provider in sun4i_usb_phy_probe(), then having a power-domains property > in the ehci/ohci nodes, pointing to the PHY node? And if yes, should > the provider be a subnode of the USB PHY node, with a separate > compatible? That sounds a bit more involved, but would have the > advantage of allowing us to specify the resets and clocks from PHY2 > there, and would look a bit cleaner than hacking them into the > other EHCI/OHCI nodes. I'm not sure we need a separate device node, we could just register the phy driver as a genpd provider, and then with an arg (so with of_genpd_add_provider_onecell?) the index of the USB controller we want to power up. > I would not touch the existing SoCs (even though it seems to apply to > them as well, just not in the exact same way), but I can give it a > try for the H616. It seems like the other SIDDQ bits (in the other > PHYs) are still needed for operation, but the PD provide could actually > take care of this as well. > > Does that make sense or is this a bit over the top for just clearing an > extra bit? Using what I described above should be fairly simple, so if we can fit in an available and relevant abstraction, yeah, I guess :) Maxime [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2021-06-07 13:23 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-19 10:41 [PATCH v6 00/17] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara 2021-05-19 10:41 ` [PATCH v6 01/17] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ) Andre Przywara 2021-05-21 1:39 ` Rob Herring 2021-05-22 14:46 ` Samuel Holland 2021-05-23 0:01 ` Andre Przywara 2021-05-19 10:41 ` [PATCH v6 02/17] mfd: axp20x: Allow AXP 806 chips without interrupt lines Andre Przywara 2021-05-19 15:01 ` Lee Jones 2021-05-19 10:41 ` [PATCH v6 03/17] dt-bindings: rtc: sun6i: Add H616 compatible string Andre Przywara 2021-05-21 1:39 ` Rob Herring 2021-05-21 2:37 ` Samuel Holland 2021-06-07 12:59 ` Andre Przywara 2021-06-08 4:23 ` Samuel Holland 2021-06-15 12:24 ` Andre Przywara 2021-06-16 9:07 ` Maxime Ripard 2021-06-16 11:28 ` Andre Przywara 2021-05-19 10:41 ` [PATCH v6 04/17] rtc: sun6i: Add support for linear day storage Andre Przywara 2021-05-22 7:26 ` Jernej Škrabec 2021-05-19 10:41 ` [PATCH v6 05/17] rtc: sun6i: Add Allwinner H616 support Andre Przywara 2021-05-22 7:29 ` Jernej Škrabec 2021-05-23 0:06 ` Andre Przywara 2021-05-19 10:41 ` [PATCH v6 06/17] dt-bindings: net: sun8i-emac: Add H616 compatible string Andre Przywara 2021-05-21 1:40 ` Rob Herring 2021-05-19 10:41 ` [PATCH v6 07/17] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara 2021-05-19 10:41 ` [PATCH v6 08/17] dt-bindings: usb: Add H616 compatible string Andre Przywara 2021-05-21 1:40 ` Rob Herring 2021-05-19 10:41 ` [PATCH v6 09/17] dt-bindings: usb: sunxi-musb: " Andre Przywara 2021-05-21 1:40 ` Rob Herring 2021-05-19 10:41 ` [PATCH v6 10/17] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Andre Przywara 2021-05-19 10:41 ` [PATCH v6 11/17] phy: sun4i-usb: Allow reset line to be shared Andre Przywara 2021-05-19 10:41 ` [PATCH v6 12/17] phy: sun4i-usb: Introduce port2 SIDDQ quirk Andre Przywara 2021-05-24 11:59 ` Maxime Ripard 2021-05-24 12:51 ` Jernej Škrabec 2021-05-25 11:29 ` Andre Przywara 2021-06-07 13:22 ` Maxime Ripard [this message] 2021-06-07 14:17 ` Andre Przywara 2021-06-07 14:26 ` [linux-sunxi] " Chen-Yu Tsai 2021-06-14 0:20 ` Andre Przywara 2021-05-19 10:41 ` [PATCH v6 13/17] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara 2021-05-19 10:41 ` [PATCH v6 14/17] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara 2021-05-24 12:02 ` Maxime Ripard 2021-06-07 12:59 ` Andre Przywara 2021-05-19 10:41 ` [PATCH v6 15/17] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara 2021-05-19 10:41 ` [PATCH v6 16/17] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Andre Przywara 2021-05-19 10:41 ` [PATCH v6 17/17] arm64: dts: allwinner: h616: Add X96 Mate TV box support Andre Przywara 2021-05-22 7:32 ` Jernej Škrabec
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