From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mslow1.mail.gandi.net (mslow1.mail.gandi.net [217.70.178.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67E7F2FAF; Fri, 10 Sep 2021 18:46:36 +0000 (UTC) Received: from relay10.mail.gandi.net (unknown [217.70.178.230]) by mslow1.mail.gandi.net (Postfix) with ESMTP id DD75DD4C23; Fri, 10 Sep 2021 18:42:23 +0000 (UTC) Received: (Authenticated sender: paul.kocialkowski@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 24D2D240004; Fri, 10 Sep 2021 18:42:14 +0000 (UTC) From: Paul Kocialkowski To: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Cc: Yong Deng , Mauro Carvalho Chehab , Rob Herring , Maxime Ripard , Sakari Ailus , Hans Verkuil , Chen-Yu Tsai , Jernej Skrabec , Paul Kocialkowski , Greg Kroah-Hartman , Helen Koike , Laurent Pinchart , Thomas Petazzoni Subject: [PATCH 01/22] clk: sunxi-ng: v3s: Make the ISP PLL clock public Date: Fri, 10 Sep 2021 20:41:26 +0200 Message-Id: <20210910184147.336618-2-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210910184147.336618-1-paul.kocialkowski@bootlin.com> References: <20210910184147.336618-1-paul.kocialkowski@bootlin.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In order to reparent the CSI module clock to the ISP PLL via device-tree, export the ISP PLL clock declaration in the public device-tree header. Details regarding why the CSI module clock is best parented to the ISP PLL are provided in the related commit. Signed-off-by: Paul Kocialkowski --- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 1 - include/dt-bindings/clock/sun8i-v3s-ccu.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h index 108eeeedcbf7..48e7e2b9fcf8 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h @@ -23,7 +23,6 @@ #define CLK_PLL_DDR0 8 #define CLK_PLL_PERIPH0 9 #define CLK_PLL_PERIPH0_2X 10 -#define CLK_PLL_ISP 11 #define CLK_PLL_PERIPH1 12 /* Reserve one number for not implemented and not used PLL_DDR1 */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h index 014ac6123d17..75f15e2d5404 100644 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h @@ -46,6 +46,7 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ #define _DT_BINDINGS_CLK_SUN8I_V3S_H_ +#define CLK_PLL_ISP 11 #define CLK_CPU 14 #define CLK_BUS_CE 20 -- 2.32.0