From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from wnew4-smtp.messagingengine.com (wnew4-smtp.messagingengine.com [64.147.123.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D22063C26 for ; Thu, 22 Sep 2022 14:28:06 +0000 (UTC) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.west.internal (Postfix) with ESMTP id AD6282B05B32; Thu, 22 Sep 2022 10:28:03 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Thu, 22 Sep 2022 10:28:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h=cc :cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1663856883; x= 1663864083; bh=0h+j4Ml235vzzhk4vbz+WoFhzY0sO9zK12Ov1UnPsu4=; b=S FZ2SNztZYY3YCcMvY9vU8Fgp9KqOhqXb15Yv+rP4F20N2IB+r2FOGUnaVfvxeCA5 Qs5T0iq8Qxt2gaJWx3dfD4AromirYmJfeztL91DVw0sJWUvsSkS6PoZAy3d7RdLB WET8r3vliStt9LpAeIU6whif9xRrEcO25hMQ30gKvXzfGYL9NV3US+3sHyggkzyw uNDkyOvOPE4e0nsw31ZUMw1vTahmLowaMOjBSS+BZ02wZc/h3X9hOei9vP3iCkuD j9kPeUqWYihzmL6GS2MRi3Uiw+22Yb6eQmTWweqObpWviMxHa1qTBCykhKuU7AWF tMr5v0zeBVpgxZGZ0lOaQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1663856883; x= 1663864083; bh=0h+j4Ml235vzzhk4vbz+WoFhzY0sO9zK12Ov1UnPsu4=; b=C xObU6mMlJxh0xcyUVe0lAfXA03pbupq3cG9zYOXnX8OmH7td8dTes8keWJdOrvKv m79YxYTwu3fVFyRbYX6Anz9qIn3yLBOs5z0+OFExR7/oTYK+lnAjYGN/DuHquIpA gbYZpy33igVSGf8kLtcDpRSJ8bDFxNh/WmtD9j5kPNOgXZKk0zm7Eo9phve1T/7S fnvVfPEI7sFDGYKE/5RkNnM+9gNnEPxQTO08iIlIR9P7yczHq1wnDb9uN098qMQy Al0x05A/rxQHzEHWVjASfPZEdm33gxu/auFNblF4f1HJABD1dzDq73TstZxlY6Cb +XGRVoX2PwW0YVpkaKwjA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrfeefgedgudejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephfffufggtgfgkfhfjgfvvefosehtkeertdertdejnecuhfhrohhmpeforgig ihhmvgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrf grthhtvghrnhepudduudfhveejteefgedvffdvvedvjedugedukeejhedtlefhffevtefh jeeltdevnecuvehluhhsthgvrhfuihiivgepfeenucfrrghrrghmpehmrghilhhfrhhomh epmhgrgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Feedback-ID: i8771445c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 22 Sep 2022 10:28:01 -0400 (EDT) From: Maxime Ripard Date: Thu, 22 Sep 2022 16:25:38 +0200 Subject: [PATCH v2 21/33] drm/connector: Add pixel clock to cmdline mode Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20220728-rpi-analog-tv-properties-v2-21-f733a0ed9f90@cerno.tech> References: <20220728-rpi-analog-tv-properties-v2-0-f733a0ed9f90@cerno.tech> In-Reply-To: <20220728-rpi-analog-tv-properties-v2-0-f733a0ed9f90@cerno.tech> To: Jernej Skrabec , Rodrigo Vivi , Ben Skeggs , David Airlie , Maxime Ripard , Joonas Lahtinen , Emma Anholt , Karol Herbst , Samuel Holland , Jani Nikula , Thomas Zimmermann , Daniel Vetter , Lyude Paul , Maarten Lankhorst , Tvrtko Ursulin , Chen-Yu Tsai Cc: Hans de Goede , nouveau@lists.freedesktop.org, Geert Uytterhoeven , Dave Stevenson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Phil Elwell , intel-gfx@lists.freedesktop.org, Noralf Trønnes , Dom Cobley , linux-sunxi@lists.linux.dev, Maxime Ripard , Mateusz Kwiatkowski , dri-devel@lists.freedesktop.org X-Mailer: b4 0.10.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2051; i=maxime@cerno.tech; h=from:subject:message-id; bh=rxoD3Af1weJFe2uj/nLNvKWNvmy0Jf/ctDPA3MS5OG0=; b=owGbwMvMwCX2+D1vfrpE4FHG02pJDMk6BYFzp3Yzxmc6Vy27uMBAa8rKkPJUx0sl609r/w9vkb/y +uf5jlIWBjEuBlkxRZYYYfMlcadmve5k45sHM4eVCWQIAxenAEzknBTDHz57x5nmH9UKKsN+5azbaq 7L+bzp3VUV7drL85fUhPy+c5mRYfKaG15zJp5WUFz0eeMD/o3Ns/JXBj1xsfm4QEVfQuiLMxMA X-Developer-Key: i=maxime@cerno.tech; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D We'll need to get the pixel clock to generate proper display modes for all the current named modes. Let's add it to struct drm_cmdline_mode and fill it when parsing the named mode. Signed-off-by: Maxime Ripard diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 5d8b6a0d96f3..eb3c4e596c67 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -2226,22 +2226,24 @@ static int drm_mode_parse_cmdline_options(const char *str, struct drm_named_mode { const char *name; + unsigned int pixel_clock_khz; unsigned int xres; unsigned int yres; unsigned int flags; }; -#define NAMED_MODE(_name, _x, _y, _flags) \ +#define NAMED_MODE(_name, _pclk, _x, _y, _flags) \ { \ .name = _name, \ + .pixel_clock_khz = _pclk, \ .xres = _x, \ .yres = _y, \ .flags = _flags, \ } static const struct drm_named_mode drm_named_modes[] = { - NAMED_MODE("NTSC", 720, 480, DRM_MODE_FLAG_INTERLACE), - NAMED_MODE("PAL", 720, 576, DRM_MODE_FLAG_INTERLACE), + NAMED_MODE("NTSC", 13500, 720, 480, DRM_MODE_FLAG_INTERLACE), + NAMED_MODE("PAL", 13500, 720, 576, DRM_MODE_FLAG_INTERLACE), }; static int drm_mode_parse_cmdline_named_mode(const char *name, @@ -2286,6 +2288,7 @@ static int drm_mode_parse_cmdline_named_mode(const char *name, continue; strcpy(cmdline_mode->name, mode->name); + cmdline_mode->pixel_clock = mode->pixel_clock_khz; cmdline_mode->xres = mode->xres; cmdline_mode->yres = mode->yres; cmdline_mode->interlace = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index fffacbfd0a45..80e19efb3f42 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -1279,6 +1279,13 @@ struct drm_cmdline_mode { */ bool bpp_specified; + /** + * @pixel_clock: + * + * Pixel Clock in kHz. Optional. + */ + unsigned int pixel_clock; + /** * @xres: * -- b4 0.10.0