From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-media@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Maxime Ripard <mripard@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Subject: [PATCH v6 5/7] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
Date: Sat, 24 Sep 2022 17:28:18 +0200 [thread overview]
Message-ID: <20220924152820.77149-6-paul.kocialkowski@bootlin.com> (raw)
In-Reply-To: <20220924152820.77149-1-paul.kocialkowski@bootlin.com>
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It is connected to the only CSI
receiver with a fwnode graph link. Note that the CSI receiver supports
both this MIPI CSI-2 source and a parallel source.
An empty port with a label for the MIPI CSI-2 sensor input is also
defined for convenience.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 43 +++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 82fdb04122ca..bbe01877a938 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1062,6 +1062,49 @@ csi: camera@1cb0000 {
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi_in_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_out_csi>;
+ };
+ };
+ };
+ };
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-a83t-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_MIPI_CSI>,
+ <&ccu CLK_CSI_MISC>;
+ clock-names = "bus", "mod", "mipi", "misc";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi: endpoint {
+ remote-endpoint = <&csi_in_mipi_csi2>;
+ };
+ };
+ };
};
hdmi: hdmi@1ee0000 {
--
2.37.3
next prev parent reply other threads:[~2022-09-24 15:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-24 15:28 [PATCH v6 0/7] Allwinner A31/A83T MIPI CSI-2 and A31 ISP / Platform Support Paul Kocialkowski
2022-09-24 15:28 ` [PATCH v6 1/7] clk: sunxi-ng: v3s: Export MBUS and DRAM clocks to the public header Paul Kocialkowski
2022-09-24 15:28 ` [PATCH v6 2/7] ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect Paul Kocialkowski
2022-09-24 15:28 ` [PATCH v6 3/7] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Paul Kocialkowski
2022-09-24 15:28 ` [PATCH v6 4/7] ARM: dts: sun8i: v3s: Add support for the ISP Paul Kocialkowski
2022-09-24 15:28 ` Paul Kocialkowski [this message]
2022-09-24 15:28 ` [PATCH v6 6/7] ARM: dts: sun8i-a83t: Add BananaPi M3 OV5640 camera overlay Paul Kocialkowski
2022-09-24 15:28 ` [PATCH v6 7/7] ARM: dts: sun8i-a83t: Add BananaPi M3 OV8865 " Paul Kocialkowski
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