From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96BA07F; Tue, 3 Jan 2023 01:09:16 +0000 (UTC) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.west.internal (Postfix) with ESMTP id 07CFF3200919; Mon, 2 Jan 2023 20:09:14 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute6.internal (MEProxy); Mon, 02 Jan 2023 20:09:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm3; t=1672708154; x=1672794554; bh=l3 3byjN96tAFT91WzVSv7uBqAlUyhhwrwVPAOp/DxlI=; b=cUBLPZjztaJPEF/tEF eXnYxSk3QYC4X9Z7BNWWtKNjLeMXIICX3Z0F8srYK52u98ILXKIAd8ey6+qiX+2/ CCjS38MZ8Oe+mD2bKi4MAGhwnVkT3B9toQo1K9iJowu5tTZG2k97iHSKAnbB5/Jr ke2GtIwXCgCdTv3mcZAC5/B0XRLjz3OJvSCueGp7HtFYI5nJzW1M+rEgNePKjwt+ 1JpAKKyNSlpHCfgUifkjt+vrUsCE8D9ExCMld5D4SiccVrOLbsjmmIlCmYP/1n/a oJkSowd45RKHw7EOYQcZgaLe7UgxoBTS6CEczexSaGjrIbnpgcpS3XgRVgeskRTc ZPFQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; t=1672708154; x=1672794554; bh=l33byjN96tAFT 91WzVSv7uBqAlUyhhwrwVPAOp/DxlI=; b=o4pb0s46K9RCUY30Fk6zVEKZDK0lT JnqzFQvbGCV95Q4cwbpolMY8oC7geSKBCkCT/zx1IY5on+go50zWThlMBK6iUhha mo850IGtZegHv5RvI74j/eHf38uCTQRfnU3wJy6Bcl/BTiLoZBmzmGnLFFdm1zTn Ogx4W7OaNakzafipaZcj0y2ttLazg6HwIFGJioYA75B3ywDWBepeEQWH6PqAXjyJ 2SDLMjvaa6rw7jliJ3nJsUraewPELG4b6UnNIKLYaeKIC4pXj4jNpSsiEOqdi8mM 73ZnvyMUw7evkNB+jW1rsWE3mlVf7C8suf7LVlBRcHw6jvdfF2zuJG7bw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrjeefgdeffecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpedukeetueduhedtleetvefguddvvdejhfefudelgfduveeggeehgfdu feeitdevteenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 2 Jan 2023 20:09:13 -0500 (EST) From: Samuel Holland To: Joerg Roedel , Will Deacon , Robin Murphy , Chen-Yu Tsai , Jernej Skrabec , Krzysztof Kozlowski , Rob Herring Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Maxime Ripard , Samuel Holland Subject: [PATCH v2 3/6] iommu/sun50i: Keep the bypass register up to date Date: Mon, 2 Jan 2023 19:09:00 -0600 Message-Id: <20230103010903.11181-4-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230103010903.11181-1-samuel@sholland.org> References: <20230103010903.11181-1-samuel@sholland.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Currently, the IOMMU driver leaves the bypass register at its default value. The H6 variant of the hardware disables bypass by default. So once the first device is attached to the IOMMU, translation is enabled for all masters, even those not attached to an IOMMU group/domain. On the other hand, the D1 hardware variant enables bypass by default, so keeping the default value prevents the IOMMU from functioning entirely. Fixes: 4100b8c229b3 ("iommu: Add Allwinner H6 IOMMU driver") Signed-off-by: Samuel Holland --- Changes in v2: - Set bypass based on attached devices instead of using a fixed value drivers/iommu/sun50i-iommu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 3757d5a18318..a3a462933c62 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -441,6 +441,9 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu) spin_lock_irqsave(&iommu->iommu_lock, flags); + iommu_write(iommu, IOMMU_BYPASS_REG, + ~atomic_read(&sun50i_domain->masters)); + iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma); iommu_write(iommu, IOMMU_TLB_PREFETCH_REG, IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) | @@ -755,6 +758,17 @@ static void sun50i_iommu_detach_domain(struct sun50i_iommu *iommu, iommu->domain = NULL; } +static void sun50i_iommu_update_masters(struct sun50i_iommu *iommu, + struct sun50i_iommu_domain *sun50i_domain) +{ + unsigned long flags; + + spin_lock_irqsave(&iommu->iommu_lock, flags); + iommu_write(iommu, IOMMU_BYPASS_REG, + ~atomic_read(&sun50i_domain->masters)); + spin_unlock_irqrestore(&iommu->iommu_lock, flags); +} + static void sun50i_iommu_detach_device(struct iommu_domain *domain, struct device *dev) { @@ -770,6 +784,8 @@ static void sun50i_iommu_detach_device(struct iommu_domain *domain, if (atomic_fetch_andnot(masters, &sun50i_domain->masters) == masters) sun50i_iommu_detach_domain(iommu, sun50i_domain); + else + sun50i_iommu_update_masters(iommu, sun50i_domain); } static int sun50i_iommu_attach_device(struct iommu_domain *domain, @@ -791,6 +807,8 @@ static int sun50i_iommu_attach_device(struct iommu_domain *domain, if (atomic_fetch_or(masters, &sun50i_domain->masters) == 0) sun50i_iommu_attach_domain(iommu, sun50i_domain); + else + sun50i_iommu_update_masters(iommu, sun50i_domain); return 0; } -- 2.37.4