From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C595C6AA6 for ; Mon, 28 Aug 2023 06:34:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1693204448; x=1724740448; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=aCl90sVW5QNut/R0WQeqfLh8sCRLNOIav5lRzT5tZqI=; b=yv1KdYfRbS2JnHBRAx1v0/1BuGNxMFM2atcislDlVz014qLcQMbqsBiX fjY/stVfulkn7qnshiIj1zTWzpBTBIzHy8Z+JR+Z8XEeCB2atD/9QrQMI SX5ox2lrwd8kjPAXuiymCAe8bX6ZxW8MU3SqciG3sNSvPHmzc5t1MZqpB HYGxa8sies9ZSBi+BtPE+SBriPZo+fi+6I5XSf1XzqAfXZHfLTRxgn8u7 MHY+CSNem1OdGIJlnRCW8BLhV2i1/vmV11ijqrifa8YYidYs/JY+ID/DO BygRJBAg3WzDf8jkbz3+1ifzfW42kjZu2TLGRcjKGqYlvC7kqTBtRQmkE A==; X-IronPort-AV: E=Sophos;i="6.02,207,1688454000"; d="asc'?scan'208";a="168600219" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Aug 2023 23:33:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sun, 27 Aug 2023 23:33:49 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Sun, 27 Aug 2023 23:33:46 -0700 Date: Mon, 28 Aug 2023 07:33:04 +0100 From: Conor Dooley To: Inochi Amaoto CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Heiko Stuebner , Wei Fu , Pei Chen , Wenhan Chen , Guo Ren , , , , , Subject: Re: [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node Message-ID: <20230828-cupid-muck-130c4ef218f6@wendy> References: Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="DSHXjya6oD0FU0CL" Content-Disposition: inline In-Reply-To: --DSHXjya6oD0FU0CL Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote: > D1 has several pmu events supported by opensbi. > These events can be used by perf for profiling. >=20 > Signed-off-by: Inochi Amaoto > Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf > Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/= gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 > --- > changed from v3: > 1. remove wrong event mapping of 0x0000a > 2. add reference url of c906 events implementation (D1 only support events > described in R1S0 user manual, but event mapping is the same) Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT. Acked-by: Conor Dooley Thanks, Conor. >=20 > changed from v2: > 1. move pmu node from /soc to / to avoid warnings when checking. >=20 > The meaning of T-HEAD events can be found in this pending patch: > https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C2177= 7BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com >=20 > The patch above also provides a example that shows how to setup > environment and use perf with T-HEAD events. > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) >=20 > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/b= oot/dts/allwinner/sun20i-d1s.dtsi > index 8275630af977..53a984d78e3f 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 { > #interrupt-cells =3D <2>; > }; > }; > + > + pmu { > + compatible =3D "riscv,pmu"; > + riscv,event-to-mhpmcounters =3D > + <0x00003 0x00003 0x00000008>, > + <0x00004 0x00004 0x00000010>, > + <0x00005 0x00005 0x00000200>, > + <0x00006 0x00006 0x00000100>, > + <0x10000 0x10000 0x00004000>, > + <0x10001 0x10001 0x00008000>, > + <0x10002 0x10002 0x00010000>, > + <0x10003 0x10003 0x00020000>, > + <0x10019 0x10019 0x00000040>, > + <0x10021 0x10021 0x00000020>; > + riscv,event-to-mhpmevent =3D > + <0x00003 0x00000000 0x00000001>, > + <0x00004 0x00000000 0x00000002>, > + <0x00005 0x00000000 0x00000007>, > + <0x00006 0x00000000 0x00000006>, > + <0x10000 0x00000000 0x0000000c>, > + <0x10001 0x00000000 0x0000000d>, > + <0x10002 0x00000000 0x0000000e>, > + <0x10003 0x00000000 0x0000000f>, > + <0x10019 0x00000000 0x00000004>, > + <0x10021 0x00000000 0x00000003>; > + riscv,raw-event-to-mhpmcounters =3D > + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, > + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, > + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, > + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, > + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, > + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, > + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, > + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, > + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, > + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, > + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, > + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > + }; > }; > -- > 2.42.0 >=20 --DSHXjya6oD0FU0CL Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZOw/nQAKCRB4tDGHoIJi 0lubAQDUXtFzd006E4QcDgB8++nyjK7XHOdcyJ8gxq6vr3ozeAEA4kcSKZeNq6ln Eeq59+bZ7kF7PhKl1/BFMaJVgBv/Rwg= =Vm8G -----END PGP SIGNATURE----- --DSHXjya6oD0FU0CL--