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[82.149.1.172]) by smtp.gmail.com with ESMTPSA id j7-20020a05600c190700b003a342933727sm3814303wmq.3.2022.09.08.09.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 09:51:39 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: =?ISO-8859-1?Q?Cl=E9ment_P=E9ron?= Cc: Chen-Yu Tsai , Samuel Holland , Rob Herring , Krzysztof Kozlowski , devicetree , linux-arm-kernel , linux-sunxi@lists.linux.dev, linux-kernel , dri-devel Subject: Re: Re: Re: [PATCH v4 3/5] arm64: dts: allwinner: h6: Add GPU OPP table Date: Thu, 08 Sep 2022 18:51:38 +0200 Message-ID: <2313716.NG923GbCHz@kista> In-Reply-To: <1800669.atdPhlSkOF@kista> References: <20220906153034.153321-1-peron.clem@gmail.com> <1800669.atdPhlSkOF@kista> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Dne =C4=8Detrtek, 08. september 2022 ob 18:26:31 CEST je Jernej =C5=A0krabe= c napisal(a): > Dne torek, 06. september 2022 ob 21:26:34 CEST je Cl=C3=A9ment P=C3=A9ron= napisal(a): > > Hi Jernej, > >=20 > > On Tue, 6 Sept 2022 at 21:10, Jernej =C5=A0krabec >=20 > wrote: > > > Dne torek, 06. september 2022 ob 17:30:32 CEST je Cl=C3=A9ment P=C3= =A9ron >=20 > napisal(a): > > > > Add an Operating Performance Points table for the GPU to > > > > enable Dynamic Voltage & Frequency Scaling on the H6. > > > >=20 > > > > The voltage range is set with minimal voltage set to the target > > > > and the maximal voltage set to 1.2V. This allow DVFS framework to > > > > work properly on board with fixed regulator. > > > >=20 > > > > Signed-off-by: Cl=C3=A9ment P=C3=A9ron > > > > --- > > > >=20 > > > > .../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi | 87 > > > > +++++++++++++++++++ > > > > 1 file changed, 87 insertions(+) > > > > create mode 100644 > > > > arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi > > > >=20 > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi > > > > b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi new file mode > > > > 100644 > > > > index 000000000000..b48049c4fc85 > > > > --- /dev/null > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi > > > > @@ -0,0 +1,87 @@ > > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > > > +// Copyright (C) 2022 Cl=C3=A9ment P=C3=A9ron > > > > + > > > > +/ { > > > > + gpu_opp_table: opp-table-gpu { > > > > + compatible =3D "operating-points-v2"; > > > > + > > > > + opp-216000000 { > > > > + opp-hz =3D /bits/ 64 <216000000>; > > > > + opp-microvolt =3D <810000 810000 1200000>; > > > > + }; > > > > + > > > > + opp-264000000 { > > > > + opp-hz =3D /bits/ 64 <264000000>; > > > > + opp-microvolt =3D <810000 810000 1200000>; > > > > + }; > > >=20 > > > As mentioned in clock patch review, rates below 288 MHz are deemed > > > unstable on GPU PLL by vendor GPU kernel driver. At least in the BSP > > > version that I have. Did you test these points? If not, better to drop > > > them. > >=20 > > I changed the governor to userspace and set the freq to 216MHz / 264MHz > > Run glmark2 and didn't observe any glitch nor issue. > >=20 > > I'm not sure if it's enough to say it's stable but I didn't observe > > any strange behavior. >=20 > Ok then. >=20 > Forgot to ask, where did you get 1.2 V as an upper limit? H6 datasheet li= sts > max. GPU voltage as 1.08 V. To answer my own question, absolute max. voltage is 1.3 V, so 1.2 V is stil= l=20 somewhat acceptable and in practice, fixed regulator on Tanix TX6 board is= =20 around 1.12 V. Boards with PMIC can set lower voltage anyway. All good. Acked-by: Jernej Skrabec =20 Best regards, Jernej =20 > > Regards, > > Clement > >=20 > > > Best regards, > > > Jernej > > >=20 > > > > + > > > > + opp-312000000 { > > > > + opp-hz =3D /bits/ 64 <312000000>; > > > > + opp-microvolt =3D <810000 810000 1200000>; > > > > + }; > > > > + > > > > + opp-336000000 { > > > > + opp-hz =3D /bits/ 64 <336000000>; > > > > + opp-microvolt =3D <810000 810000 1200000>; > > > > + }; > > > > + > > > > + opp-360000000 { > > > > + opp-hz =3D /bits/ 64 <360000000>; > > > > + opp-microvolt =3D <820000 820000 1200000>; > > > > + }; > > > > + > > > > + opp-384000000 { > > > > + opp-hz =3D /bits/ 64 <384000000>; > > > > + opp-microvolt =3D <830000 830000 1200000>; > > > > + }; > > > > + > > > > + opp-408000000 { > > > > + opp-hz =3D /bits/ 64 <408000000>; > > > > + opp-microvolt =3D <840000 840000 1200000>; > > > > + }; > > > > + > > > > + opp-420000000 { > > > > + opp-hz =3D /bits/ 64 <420000000>; > > > > + opp-microvolt =3D <850000 850000 1200000>; > > > > + }; > > > > + > > > > + opp-432000000 { > > > > + opp-hz =3D /bits/ 64 <432000000>; > > > > + opp-microvolt =3D <860000 860000 1200000>; > > > > + }; > > > > + > > > > + opp-456000000 { > > > > + opp-hz =3D /bits/ 64 <456000000>; > > > > + opp-microvolt =3D <870000 870000 1200000>; > > > > + }; > > > > + > > > > + opp-504000000 { > > > > + opp-hz =3D /bits/ 64 <504000000>; > > > > + opp-microvolt =3D <890000 890000 1200000>; > > > > + }; > > > > + > > > > + opp-540000000 { > > > > + opp-hz =3D /bits/ 64 <540000000>; > > > > + opp-microvolt =3D <910000 910000 1200000>; > > > > + }; > > > > + > > > > + opp-576000000 { > > > > + opp-hz =3D /bits/ 64 <576000000>; > > > > + opp-microvolt =3D <930000 930000 1200000>; > > > > + }; > > > > + > > > > + opp-624000000 { > > > > + opp-hz =3D /bits/ 64 <624000000>; > > > > + opp-microvolt =3D <950000 950000 1200000>; > > > > + }; > > > > + > > > > + opp-756000000 { > > > > + opp-hz =3D /bits/ 64 <756000000>; > > > > + opp-microvolt =3D <1040000 1040000 1200000>; > > > > + }; > > > > + }; > > > > +}; > > > > + > > > > +&gpu { > > > > + operating-points-v2 =3D <&gpu_opp_table>; > > > > +}; > > > > -- > > > > 2.34.1