From: Jaehoon Chung <jh80.chung@samsung.com>
To: Andre Przywara <andre.przywara@arm.com>,
Jagan Teki <jagan@amarulasolutions.com>,
Peng Fan <peng.fan@nxp.com>
Cc: u-boot@lists.denx.de, Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Ondrej Jirman <megous@megous.com>,
linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 4/8] mmc: sunxi: Cleanup "new timing mode" selection
Date: Tue, 25 May 2021 10:43:05 +0900 [thread overview]
Message-ID: <7d75fbee-22d1-0c1d-7211-fe371f9cbe3c@samsung.com> (raw)
In-Reply-To: <20210524233029.16417-5-andre.przywara@arm.com>
On 5/25/21 8:30 AM, Andre Przywara wrote:
> Among the SoCs using the "new timing mode", only the A83T needs to
> explicitly switch to that mode.
>
> By just defining the symbol for that one odd A83T bit to 0 for any other
> SoCs, we can always OR that in, and save the confusing nested #ifdefs.
>
> Clean up the also confusing new_mode setting on the way.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/sunxi_mmc.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index bc68debdad6..33cedb4edba 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -23,6 +23,10 @@
> #include <asm-generic/gpio.h>
> #include <linux/delay.h>
>
> +#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
> +#define CCM_MMC_CTRL_MODE_SEL_NEW 0
> +#endif
> +
> struct sunxi_mmc_plat {
> struct mmc_config cfg;
> struct mmc mmc;
> @@ -102,13 +106,10 @@ static int mmc_resource_init(int sdc_no)
> static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
> {
> unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
> - bool new_mode = true;
> + bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
> bool calibrate = false;
> u32 val = 0;
>
> - if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
> - new_mode = false;
> -
> /* A83T support new mode only on eMMC */
> if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
> new_mode = false;
> @@ -176,12 +177,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
> }
>
> if (new_mode) {
> -#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
> -#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
> - val = CCM_MMC_CTRL_MODE_SEL_NEW;
> -#endif
> + val |= CCM_MMC_CTRL_MODE_SEL_NEW;
> setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
> -#endif
> } else if (!calibrate) {
> /*
> * Use hardcoded delay values if controller doesn't support
>
next prev parent reply other threads:[~2021-05-25 1:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-24 23:30 [PATCH 0/8] sunxi: mmc: Fixes and speed increase Andre Przywara
2021-05-24 23:30 ` [PATCH 1/8] mmc: sunxi: Avoid #ifdefs in delay and width setup Andre Przywara
2021-05-25 1:42 ` Jaehoon Chung
2021-05-24 23:30 ` [PATCH 2/8] mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT Andre Przywara
2021-05-25 1:43 ` Jaehoon Chung
2021-05-24 23:30 ` [PATCH 3/8] mmc: sunxi: Fix MMC clock parent selection Andre Przywara
2021-05-24 23:30 ` [PATCH 4/8] mmc: sunxi: Cleanup "new timing mode" selection Andre Przywara
2021-05-25 1:43 ` Jaehoon Chung [this message]
2021-05-24 23:30 ` [PATCH 5/8] mmc: sunxi: Enable "new timing mode" on all new SoCs Andre Przywara
2021-05-24 23:30 ` [PATCH 6/8] mmc: sunxi: Cleanup and fix self-calibration code Andre Przywara
2021-05-24 23:30 ` [PATCH 7/8] mmc: sunxi: Increase MMIO FIFO read performance Andre Przywara
2021-05-24 23:30 ` [PATCH 8/8] mmc: sunxi: Use mmc_of_parse() Andre Przywara
2021-05-25 1:43 ` Jaehoon Chung
2021-07-03 23:24 ` [PATCH 0/8] sunxi: mmc: Fixes and speed increase Andre Przywara
2021-07-04 19:56 ` Samuel Holland
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7d75fbee-22d1-0c1d-7211-fe371f9cbe3c@samsung.com \
--to=jh80.chung@samsung.com \
--cc=andre.przywara@arm.com \
--cc=jagan@amarulasolutions.com \
--cc=jernej.skrabec@gmail.com \
--cc=linux-sunxi@lists.linux.dev \
--cc=megous@megous.com \
--cc=peng.fan@nxp.com \
--cc=samuel@sholland.org \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).