From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97EFE71 for ; Thu, 20 May 2021 01:45:59 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 1D12F61353 for ; Thu, 20 May 2021 01:45:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621475159; bh=QVDdQASuS8d9nfiPodUILwkkCeDcq435J2Gdpya1/ks=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=aph4t/OpytN2td2rihSkPJpvAJmj3uRO97MpUkypnltNuu65Hws5hw0roDgsvXnoe C1rB8CAqcXJeDT4LXV44wliD6TUvEB5QZKJhEo0nKPvqU2Yg75uf/qKgwz66wnE+83 V8Oenk4Kv29uKcK56VKcJAN0cxw4AfW2JNBjtM8DCYH2Wr3nQEHgHQBPB0A4Wl1IHP A4B6iKVTsPD6rAhRBh02GZ3LYknkrvap1HdQLSa81EH8egwbdYSLzcObSKu2bHhIyM NW3kdhC4/S8F4G1/xtDqCPZVVcyLr/Gd3YI+TWCkMfNpQwHe4EdeZ/tywUm+dXO9Za OJ6M2+obNBfPQ== Received: by mail-lf1-f53.google.com with SMTP id r5so21950878lfr.5 for ; Wed, 19 May 2021 18:45:59 -0700 (PDT) X-Gm-Message-State: AOAM533wYxv4k8aXPe3Idi/83fYXDEgnX/a7iWXqv/q1YDjy62vvpqT+ BmMv6zeRv5TY5xHDOCb5LUIuNABGV8xruBdJKNE= X-Google-Smtp-Source: ABdhPJxvtxM93jgsgXbzFfEJugjs4lSYYrFCIibVxmW1z4FBvYEZG3re1CeFqZabsg3qTIpZ9JXvpLiBbrRPU2sVGHY= X-Received: by 2002:a19:ccc:: with SMTP id 195mr1668868lfm.24.1621475157363; Wed, 19 May 2021 18:45:57 -0700 (PDT) X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519064435.GA3076809@x1> <20210519065352.GA31590@lst.de> In-Reply-To: <20210519065352.GA31590@lst.de> From: Guo Ren Date: Thu, 20 May 2021 09:45:45 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support To: Christoph Hellwig Cc: Drew Fustini , Anup Patel , Palmer Dabbelt , wefu@redhat.com, lazyparser@gmail.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Paul Walmsley , Nick Kossifidis , Benjamin Koch , Matteo Croce , Wei Fu Content-Type: text/plain; charset="UTF-8" On Wed, May 19, 2021 at 2:53 PM Christoph Hellwig wrote: > > On Tue, May 18, 2021 at 11:44:35PM -0700, Drew Fustini wrote: > > This patch series looks like it might be useful for the StarFive JH7100 > > [1] [2] too as it has peripherals on a non-coherent interconnect. GMAC, > > USB and SDIO require that the L2 cache must be manually flushed after > > DMA operations if the data is intended to be shared with U74 cores [2]. > > Not too much, given that the SiFive lineage CPUs have an uncached > window, that is a totally different way to allocate uncached memory. It's a very big MIPS smell. What's the attribute of the uncached window? (uncached + strong-order/ uncached + weak, most vendors still use AXI interconnect, how to deal with a bufferable attribute?) In fact, customers' drivers use different ways to deal with DMA memory in non-coherent SOC. Most riscv SOC vendors are from ARM, so giving them the same way in DMA memory is a smart choice. So using PTE attributes is more suitable. See: https://github.com/riscv/virtual-memory/blob/main/specs/611-virtual-memory-diff.pdf 4.4.1 The draft supports custom attribute bits in PTE. Although I do not agree with uncached windows, this patchset does not conflict with SiFive uncached windows. > > > There is the RISC-V Cache Management Operation, or CMO, task group [3] > > but I am not sure if that can help the SoC's that have already been > > fabbed like the the D1 and the JH7100. > > It does, because unimplemented instructions trap into M-mode, where they > can be emulated. > > Or to summarize things. Non-coherent DMA (and not coherent as title in > this series) requires two things: > > 1) allocating chunks of memory that is marked as not cachable > 2) instructions to invalidate and/or writeback cache lines Maybe sbi_ecall (dma_sync) is enough and let the vendor deal with it in opensbi. From a hardware view, CMO instruction only could deal with one cache line, then CMO-trap is not a good idea. > > none of which currently exists in RISV-V. Hacking vendor specific > cruft into the kernel doesn't scale, as shown perfectly by this > series which requires to hard code vendor-specific non-standardized > extensions in a kernel that makes it specific to that implementation. > > What we need to do is to standardize a way to do this properly, and then > after that figure out a way to quirk in non-compliant implementations > in a way that does not harm the general kernel. -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/