From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC7D370 for ; Mon, 7 Jun 2021 06:41:27 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 925C66121D for ; Mon, 7 Jun 2021 06:41:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1623048087; bh=WJHQdy4sxhvqgS0MC5lUqEPV39/gM84OpLAauZzAMsQ=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=miti1pGf4X8JSTw+5bAKnmC6J/Oj62GADAh/qU5LGizT3e/mguJHZYM/HqQjB9JIC kYOIigfg/o2c0kby0ih2HYmQpm24HYwopDiL3sUY0tLTvmmNznCaAsgxm9GLV4Mbis mZqLvmGJc7YlE5ocLu7KjJC0SKVop1urwUZyAaQHglZKXQnQTyz1DsATFehEIwFyv3 UjfoQ5iT8ItqzGwLGejyyPOHpU5BdHQGHEMs4OdvfqtyUQhg/N/R4GEYNMQJGqzZjk 6UyPivlChb4tunck8+dpZSp+s8/dW/A9h/CokwsPzzfa40Gn2ysp0dFXDHvrn2f+dr 8QEa7lrAA4jAA== Received: by mail-lf1-f54.google.com with SMTP id i10so24445876lfj.2 for ; Sun, 06 Jun 2021 23:41:27 -0700 (PDT) X-Gm-Message-State: AOAM5304MoXBChzYsj4BNW2GQZ3Imr7Lz8aiAcN+QqtRnp7ccuWZgAg3 8+0NlAUYH6SwIy5XnKeWdi45D/qfQW9scBWmXo4= X-Google-Smtp-Source: ABdhPJzQw6LHnGrCaA99WogkWxVtNvLnTm9mlFy3domKzPtpc2G5ul39vIh3zn+wlblu5LdVLL4Gofw9oNvf17vVTj0= X-Received: by 2002:a05:6512:987:: with SMTP id w7mr10846468lft.41.1623048085938; Sun, 06 Jun 2021 23:41:25 -0700 (PDT) X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519064435.GA3076809@x1> <20210519065352.GA31590@lst.de> <29733b0931d9dd6a2f0b6919067c7efe@mailhost.ics.forth.gr> <20210607062701.GB24060@lst.de> In-Reply-To: <20210607062701.GB24060@lst.de> From: Guo Ren Date: Mon, 7 Jun 2021 14:41:14 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support To: Christoph Hellwig Cc: Nick Kossifidis , Drew Fustini , Anup Patel , Palmer Dabbelt , wefu@redhat.com, =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Paul Walmsley , Benjamin Koch , Matteo Croce , Wei Fu Content-Type: text/plain; charset="UTF-8" On Mon, Jun 7, 2021 at 2:27 PM Christoph Hellwig wrote: > > On Mon, Jun 07, 2021 at 11:19:03AM +0800, Guo Ren wrote: > > >From Linux non-coherency view, we need: > > - Non-cache + Strong Order PTE attributes to deal with drivers' DMA descriptors > > - Non-cache + weak order to deal with framebuffer drivers > > - CMO dma_sync to sync cache with DMA devices > > This is not strictly true. At the very minimum you only need cache > invalidation and writeback instructions. For example early parisc > CPUs and some m68knommu SOCs have no support for uncached areas at all, > and Linux works. But to be fair this is very painful and supports only > very limited periphals. So for modern full Linux support some uncahed > memory is advisable. But that doesn't have to be using PTE attributes. > It could also be physical memory regions that are either totally fixed Double/Triple the size of physical memory regions can't be accepted by SOC vendors, because it wastes HW resources. Some cost-down soc interconnects only have 32bit~34bit width of physical address, are you sure you could force them to expand it? (I can't) > or somewhat dynamic. How can HW implement with dynamic modifying PMA? What's the granularity? -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/