From: Guo Ren <guoren@kernel.org>
To: Nick Kossifidis <mick@ics.forth.gr>
Cc: "Christoph Hellwig" <hch@lst.de>,
"Drew Fustini" <drew@beagleboard.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
wefu@redhat.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
linux-arch <linux-arch@vger.kernel.org>,
linux-sunxi@lists.linux.dev, "Guo Ren" <guoren@linux.alibaba.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Benjamin Koch" <snowball@c3pb.de>,
"Matteo Croce" <mcroce@linux.microsoft.com>,
"Wei Fu" <tekkamanninja@gmail.com>
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support
Date: Mon, 7 Jun 2021 08:04:40 +0800 [thread overview]
Message-ID: <CAJF2gTTpSbNWS4VLHAu4XsV5-Vos=6R9MmPOx8-yzMFJu=wX4A@mail.gmail.com> (raw)
In-Reply-To: <29733b0931d9dd6a2f0b6919067c7efe@mailhost.ics.forth.gr>
On Mon, Jun 7, 2021 at 2:14 AM Nick Kossifidis <mick@ics.forth.gr> wrote:
>
> Στις 2021-05-20 04:45, Guo Ren έγραψε:
> > On Wed, May 19, 2021 at 2:53 PM Christoph Hellwig <hch@lst.de> wrote:
> >>
> >> On Tue, May 18, 2021 at 11:44:35PM -0700, Drew Fustini wrote:
> >> > This patch series looks like it might be useful for the StarFive JH7100
> >> > [1] [2] too as it has peripherals on a non-coherent interconnect. GMAC,
> >> > USB and SDIO require that the L2 cache must be manually flushed after
> >> > DMA operations if the data is intended to be shared with U74 cores [2].
> >>
> >> Not too much, given that the SiFive lineage CPUs have an uncached
> >> window, that is a totally different way to allocate uncached memory.
> > It's a very big MIPS smell. What's the attribute of the uncached
> > window? (uncached + strong-order/ uncached + weak, most vendors still
> > use AXI interconnect, how to deal with a bufferable attribute?) In
> > fact, customers' drivers use different ways to deal with DMA memory in
> > non-coherent SOC. Most riscv SOC vendors are from ARM, so giving them
> > the same way in DMA memory is a smart choice. So using PTE attributes
> > is more suitable.
> >
> > See:
> > https://github.com/riscv/virtual-memory/blob/main/specs/611-virtual-memory-diff.pdf
> > 4.4.1
> > The draft supports custom attribute bits in PTE.
> >
>
> Not only it doesn't support custom attributes on PTEs:
>
> "Bits63–54 are reserved for future standard use and must be zeroed by
> software for forward compatibility."
>
> It also goes further to say that:
>
> "if any of these bits are set, a page-fault exception is raised"
In RISC-V VM TG, A C-bit discussion is raised. So it's a comm idea to
support it.
Let Linux support custom PTE attributes won't get any side effect in practice.
IMO:
We needn't waste a bit in PTE, but the custom idea in PTE reserved
bits is necessary. Because Allwinner D1 needs custom PTE bits in
reserved bits to work around.
So I recommend just remove the "C" bit in PTE, but allow vendors to
define their own PTE attributes in reserved bits. I've found a way to
compact different PTE attributes of different vendors during the Linux
boot stage. That means we still could use One Image for all vendors in
Linux
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
next prev parent reply other threads:[~2021-06-07 0:04 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 5:04 [PATCH RFC 0/3] riscv: Add DMA_COHERENT support guoren
2021-05-19 5:04 ` [PATCH RFC 1/3] riscv: pgtable.h: Fixup _PAGE_CHG_MASK usage guoren
2021-05-19 5:04 ` [PATCH RFC 2/3] riscv: Add DMA_COHERENT for custom PTE attributes guoren
2021-05-19 5:04 ` [PATCH RFC 3/3] riscv: Add SYNC_DMA_FOR_CPU/DEVICE for DMA_COHERENT guoren
2021-05-19 6:32 ` Guo Ren
2021-05-19 5:20 ` [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Christoph Hellwig
2021-05-19 5:48 ` Guo Ren
2021-05-19 5:55 ` Christoph Hellwig
2021-05-19 6:09 ` Guo Ren
2021-05-19 6:44 ` Drew Fustini
2021-05-19 6:53 ` Christoph Hellwig
2021-05-20 1:45 ` Guo Ren
2021-05-20 5:48 ` Christoph Hellwig
2021-06-06 18:14 ` Nick Kossifidis
2021-06-07 0:04 ` Guo Ren [this message]
2021-06-07 2:16 ` Nick Kossifidis
2021-06-07 3:19 ` Guo Ren
2021-06-07 6:27 ` Christoph Hellwig
2021-06-07 6:41 ` Guo Ren
2021-06-07 6:51 ` Christoph Hellwig
2021-06-07 7:46 ` Guo Ren
2021-06-08 15:00 ` David Laight
2021-06-08 15:32 ` 'Christoph Hellwig'
2021-06-08 16:11 ` David Laight
2021-06-07 8:35 ` Nick Kossifidis
2021-06-09 3:28 ` Guo Ren
2021-06-09 6:05 ` Jisheng Zhang
2021-06-09 9:45 ` Nick Kossifidis
2021-06-09 12:43 ` Guo Ren
2021-05-19 6:05 ` Guo Ren
2021-05-19 6:06 ` Christoph Hellwig
2021-05-19 6:11 ` Guo Ren
2021-05-19 6:54 ` Drew Fustini
2021-05-19 6:56 ` Christoph Hellwig
2021-05-19 7:14 ` Anup Patel
2021-05-19 8:25 ` Damien Le Moal
2021-05-20 1:47 ` Guo Ren
2021-05-20 1:59 ` Guo Ren
2021-05-22 0:36 ` Guo Ren
2021-05-30 0:30 ` Palmer Dabbelt
2021-06-03 4:13 ` Palmer Dabbelt
2021-06-03 6:00 ` Anup Patel
2021-06-03 15:39 ` Palmer Dabbelt
2021-06-04 9:02 ` David Laight
2021-06-04 9:53 ` Arnd Bergmann
2021-06-04 14:47 ` Guo Ren
2021-06-04 16:12 ` Palmer Dabbelt
2021-06-04 21:26 ` Arnd Bergmann
2021-06-04 22:10 ` Palmer Dabbelt
2021-06-08 12:26 ` Guo Ren
2021-06-06 17:11 ` Guo Ren
2021-06-07 3:38 ` Anup Patel
2021-06-07 4:22 ` Guo Ren
2021-06-07 4:47 ` Anup Patel
2021-06-07 5:08 ` Guo Ren
2021-06-07 5:13 ` Guo Ren
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