From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f50.google.com (mail-ot1-f50.google.com [209.85.210.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05DAB71 for ; Wed, 12 May 2021 09:18:34 +0000 (UTC) Received: by mail-ot1-f50.google.com with SMTP id d25-20020a0568300459b02902f886f7dd43so6553493otc.6 for ; Wed, 12 May 2021 02:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=ilHpinXfJbBO00ILl8M3cL9co4ZLrs2Vn6MnmXJH7Ac=; b=OpYb3E4eC+El3f8COSWswjpzDbG74EZU9suX/LZaPOWAmGPxMlcl3qy6UBzSRHICf0 Y2WOguxoF8nNew/YOA4M0/WLN9WRtZxPXf8zBnnPNinvB9EQMoUxK07ivCaTWzBSuTNU Ut+yFn5yWNKnSWelekyNqx7tQ5pNtFVtjDmpN9jM87iVMLscahq2jLc6DIF4Y2Bw1WeY qsN8283JRlxYbihv+OjKa11ci0flV/XdvTleu5y/xpp5fC3c+mkFS0aZV+N4Q+67ej+m opSNyUzGiK1TMy+RtfXyM5QI4RDfECZTHlQciDgPdvNuKqoi8XfDWzfKRhMG77yBIIIr t4Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=ilHpinXfJbBO00ILl8M3cL9co4ZLrs2Vn6MnmXJH7Ac=; b=DPcnJUSxWLxySYeD5gdGqujJTCal8Xz37fhODN71cad2Iw81v8kK8elxbc2O/teXcu ePnLkPjRz2fRWvB9D6ZX3eAKAw57anYe+U83Omu5aTDSgXVnm3emOlN52y2BvVOrTSHI iIpg1PfiwaHjwYrwIADm+X0xGCjrw5KMIBFffaFRimLWCxvt/3RZb5j7OimRcXcahIhn Lgd+apdQ7yNdfAYZevVXNIayE/d80Zp+fJ9NzeiKuous1pwX15f80Wk6xTf/oDZQ+Xd8 5jELCR+BCTCRrUKTwJJdXyvaglQbFH9mDKv4veztXml79Ocxpff7G8eCxxpUDCONyf1q UqYA== X-Gm-Message-State: AOAM533CpRF+Px/6H4xPWE/9p3mHGEAevLKhNMrRwBjF70cOsKZlWHWK Wel7x1+7WPRyNM/6nmW9kNcF14BMINq3hpVgl7Y= X-Google-Smtp-Source: ABdhPJxL5e7JMKGEAMi+g54pI1yxPu1G+9tSMQnIgWLQZ0pKp4sbyHdu8tnX79kJNw/uYM4GtFc0VbCLWkaoTi0R2lE= X-Received: by 2002:a9d:e88:: with SMTP id 8mr28771453otj.239.1620811114262; Wed, 12 May 2021 02:18:34 -0700 (PDT) X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20210511220014.1945519-1-roman.beranek@prusa3d.com> <20210512044133.6yfwyluzdx6yfh4c@pengutronix.de> In-Reply-To: <20210512044133.6yfwyluzdx6yfh4c@pengutronix.de> From: Emil Lenngren Date: Wed, 12 May 2021 11:18:24 +0200 Message-ID: Subject: Re: [PATCH] pwm: sun4i: Avoid waiting until the next period To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= Cc: Roman Beranek , Thierry Reding , Lee Jones , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com, Roman Beranek Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Uwe, Den ons 12 maj 2021 kl 06:41 skrev Uwe Kleine-K=C3=B6nig : > > Hello Emil, > > On Wed, May 12, 2021 at 02:55:26AM +0200, Emil Lenngren wrote: > > Well that's one way of "solving it" ;) > > > > But on what hardware do you really need to wait until one full pulse > > cycle ends, before a disable command takes effect? > > > > On the hardware I've tested on (GR8 and V3s), it's enough to wait at > > most two clock cycles in order for it to take effect before we can > > close the gate. And with clock cycle I mean 24 MHz divided by the > > prescaler. With prescaler 1, that's 84 nanoseconds. By closing the > > gate when the pwm should be disabled, I guess we could save some > > nanoampere or microampere (is this important?) > > If I understood correctly you really have to wait longer to achieve that > the output is inactive in the disabled state. Do you talk about the same > thing? Exactly, i.e. after writing 0 to the EN bit, we don't have to wait until the current period ends before we can observe that the output signal goes to the inactive state. Simple test: 1. Set pwm interval to a long time like 2 seconds, and duty to 50%. 2. Enable clock gating. 3. Enable the pwm by writing 1 to the EN bit. 4. Observe the LED blink once per second. 5. Now at a random time write 0 to the EN bit in order to disable the pwm. Don't turn off the clock gating. 6. If you just look with the eye it appears the LED turns off immediately, regardless of when in the pulse cycle we disabled it. Just tested the above using "devmem" on a V3s. By using a large prescaler and testing some different prescalers, I've concluded that it takes at least 1 and at most 2 clock cycles before we can safely turn off the gate and be certain that the output pin has changed to disabled. It would be good if people having other hardware could confirm this is correct there as well. Please take a look at some previous material I wrote: https://lkml.org/lkml/2020/3/17/1158 https://linux-sunxi.org/PWM_Controller_Register_Guide (Observed behaviour on GR8 from NextThing) https://pastebin.com/GWrhWzPJ /Emil