From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6668070 for ; Tue, 25 May 2021 16:39:35 +0000 (UTC) Received: by mail-wr1-f49.google.com with SMTP id n2so33033247wrm.0 for ; Tue, 25 May 2021 09:39:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=GEKgoi2/bl5p1Vp5VslwoOtEKcH+XHZmWKomAsa1ah4=; b=Iz7gosRTk5IGEy3BTOerDjpxERmnYHc3S4V/cEO+bStXkiWnXSUkzx++25aTQClwsY mJaZ1QHEi0FHxZrNElSvsFwctxa9qDZQIabueuI21b5C334LCIxz3dRB3nvMkzkXFZvq h4e2qye7Xw5ea7YoRNK4ErV14YD4F8sZi7DHsXfVNFoaFe3+rYlYqjZNAFvfUYIT4dTa pnB3jIjzsL47b8sL3PSZhMW9tjLfez8lRjVa2UOlu93uo5mqMk9ikF0pVsWPUGFeKJCH 9OUNN98bvhN0dIYhq1NNoJtuXFtm13ePS7OzVgEsvsKOceozDbL20UlsaA71p7UjqUyu GhFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=GEKgoi2/bl5p1Vp5VslwoOtEKcH+XHZmWKomAsa1ah4=; b=HlD9zQlJQvUBgc7eqlo//39WaRQEQqsD/M6+zViR697YOaaV4K1RyAN3+O41kohP68 RSEhG59Meki+mUVd/P3fJH03OgYO9/x9Rm8enlf3elX887JYIpWaQbgpfAJ6kaicn7hc Gt9S1se7/IkRyMw0JWX6fhzH1+1GdJ5woVoWPqlMILDy7spHZr3E/cUNEqEp8vWhD6Ji C/2tKEghr0sXBCxxbcW3hgpmYRMv/wbJ7yQaifKebIYWS5arMnVxVViq7eGckU7F/aPs /TQskNqqqNPirtXQkgdsoip/v3juT8PBga517z4XmlgFE9Mz+oop8oFNrdYrchP8GJh6 saEQ== X-Gm-Message-State: AOAM532xEv6kGEwvBiMMkM/N8KULz4G+fEmxjiKKxad7yQ7g414VBDZw DMeIWuuITcSLqi9aNCh3Rsg= X-Google-Smtp-Source: ABdhPJwOqI8HA0KrvXSLUIa4TLMtXrZvotnrSrOccv3vDeHR28gkQLfrT+HQTPMVGpG27i7qAoV2QA== X-Received: by 2002:a5d:50c7:: with SMTP id f7mr29122996wrt.189.1621960773804; Tue, 25 May 2021 09:39:33 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id 11sm11715857wmo.24.2021.05.25.09.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 May 2021 09:39:32 -0700 (PDT) Date: Tue, 25 May 2021 18:41:00 +0200 From: Thierry Reding To: Emil Lenngren Cc: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Roman Beranek , Lee Jones , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com, Roman Beranek , Alexandre Belloni Subject: Re: [PATCH] pwm: sun4i: Avoid waiting until the next period Message-ID: References: <20210511220014.1945519-1-roman.beranek@prusa3d.com> <20210512044133.6yfwyluzdx6yfh4c@pengutronix.de> X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Zw6ChVpkyZLA/4W4" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.0.6 (98f8cb83) (2021-03-06) --Zw6ChVpkyZLA/4W4 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, May 12, 2021 at 11:18:24AM +0200, Emil Lenngren wrote: > Hi Uwe, >=20 > Den ons 12 maj 2021 kl 06:41 skrev Uwe Kleine-K=C3=B6nig > : > > > > Hello Emil, > > > > On Wed, May 12, 2021 at 02:55:26AM +0200, Emil Lenngren wrote: > > > Well that's one way of "solving it" ;) > > > > > > But on what hardware do you really need to wait until one full pulse > > > cycle ends, before a disable command takes effect? > > > > > > On the hardware I've tested on (GR8 and V3s), it's enough to wait at > > > most two clock cycles in order for it to take effect before we can > > > close the gate. And with clock cycle I mean 24 MHz divided by the > > > prescaler. With prescaler 1, that's 84 nanoseconds. By closing the > > > gate when the pwm should be disabled, I guess we could save some > > > nanoampere or microampere (is this important?) > > > > If I understood correctly you really have to wait longer to achieve that > > the output is inactive in the disabled state. Do you talk about the same > > thing? >=20 > Exactly, i.e. after writing 0 to the EN bit, we don't have to wait > until the current period ends before we can observe that the output > signal goes to the inactive state. >=20 > Simple test: >=20 > 1. Set pwm interval to a long time like 2 seconds, and duty to 50%. > 2. Enable clock gating. > 3. Enable the pwm by writing 1 to the EN bit. > 4. Observe the LED blink once per second. > 5. Now at a random time write 0 to the EN bit in order to disable the > pwm. Don't turn off the clock gating. > 6. If you just look with the eye it appears the LED turns off > immediately, regardless of when in the pulse cycle we disabled it. >=20 > Just tested the above using "devmem" on a V3s. >=20 > By using a large prescaler and testing some different prescalers, I've > concluded that it takes at least 1 and at most 2 clock cycles before > we can safely turn off the gate and be certain that the output pin has > changed to disabled. >=20 > It would be good if people having other hardware could confirm this is > correct there as well. >=20 > Please take a look at some previous material I wrote: > https://lkml.org/lkml/2020/3/17/1158 > https://linux-sunxi.org/PWM_Controller_Register_Guide (Observed > behaviour on GR8 from NextThing) > https://pastebin.com/GWrhWzPJ I'm pretty sure Alexandre at the time reported that the instantiation of the controller that he was using required waiting for the period to complete before the output went to the disabled state. It's possible that this was changed in subsequent versions of the IP, so perhaps we need to distinguish based on compatible string? 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