From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mslow1.mail.gandi.net (mslow1.mail.gandi.net [217.70.178.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24DE73FC4; Mon, 13 Sep 2021 07:50:33 +0000 (UTC) Received: from relay11.mail.gandi.net (unknown [217.70.178.231]) by mslow1.mail.gandi.net (Postfix) with ESMTP id 08D06CCFCF; Mon, 13 Sep 2021 07:44:42 +0000 (UTC) Received: (Authenticated sender: paul.kocialkowski@bootlin.com) by relay11.mail.gandi.net (Postfix) with ESMTPSA id 6AD0F100018; Mon, 13 Sep 2021 07:44:23 +0000 (UTC) Date: Mon, 13 Sep 2021 09:44:22 +0200 From: Paul Kocialkowski To: Samuel Holland Cc: Yong Deng , Mauro Carvalho Chehab , Rob Herring , Maxime Ripard , Sakari Ailus , Hans Verkuil , Chen-Yu Tsai , Jernej Skrabec , Greg Kroah-Hartman , Helen Koike , Laurent Pinchart , Thomas Petazzoni , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH 09/22] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Message-ID: References: <20210910184147.336618-1-paul.kocialkowski@bootlin.com> <20210910184147.336618-10-paul.kocialkowski@bootlin.com> <483288cb-d9fa-4581-7986-d15c4aa27769@sholland.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="QZVQzP+VTAJydr5U" Content-Disposition: inline In-Reply-To: <483288cb-d9fa-4581-7986-d15c4aa27769@sholland.org> --QZVQzP+VTAJydr5U Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Samuel, On Fri 10 Sep 21, 21:32, Samuel Holland wrote: > On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > > MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge > > controller. The controller uses a separate D-PHY, which is the same > > that is otherwise used for MIPI DSI, but used in Rx mode. > >=20 > > On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does > > not have access to any parallel interface pins. > >=20 > > Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to > > support the MIPI CSI-2 interface. > >=20 > > Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 > > even when no sensor is connected. This will result in a probe failure > > for the controller as long as no sensor is connected but this is fine > > since no other interface is available. > >=20 > > Signed-off-by: Paul Kocialkowski > > --- > > arch/arm/boot/dts/sun8i-v3s.dtsi | 72 ++++++++++++++++++++++++++++++++ > > 1 file changed, 72 insertions(+) > >=20 > > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i= -v3s.dtsi > > index a77b63362a1d..ec7fa6459547 100644 > > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > > @@ -612,6 +612,34 @@ spi0: spi@1c68000 { > > #size-cells =3D <0>; > > }; > > =20 > > + csi0: camera@1cb0000 { > > + compatible =3D "allwinner,sun8i-v3s-csi"; > > + reg =3D <0x01cb0000 0x1000>; > > + interrupts =3D ; > > + clocks =3D <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI1_SCLK>, > > + <&ccu CLK_DRAM_CSI>; > > + clock-names =3D "bus", "mod", "ram"; > > + resets =3D <&ccu RST_BUS_CSI>; > > + status =3D "disabled"; > > + > > + assigned-clocks =3D <&ccu CLK_CSI1_SCLK>; > > + assigned-clock-parents =3D <&ccu CLK_PLL_ISP>; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + port@1 { > > + reg =3D <1>; > > + > > + csi0_in_mipi_csi2: endpoint { > > + remote-endpoint =3D <&mipi_csi2_out_csi0>; > > + }; > > + }; > > + }; > > + }; > > + > > csi1: camera@1cb4000 { > > compatible =3D "allwinner,sun8i-v3s-csi"; > > reg =3D <0x01cb4000 0x3000>; >=20 > All of the new nodes should be added above this one, to maintain unit > address order. Good catch, this was an overlook on my side. Thanks, Paul > Regards, > Samuel >=20 > > @@ -637,5 +665,49 @@ gic: interrupt-controller@1c81000 { > > #interrupt-cells =3D <3>; > > interrupts =3D ; > > }; > > + > > + mipi_csi2: csi@1cb1000 { > > + compatible =3D "allwinner,sun8i-v3s-mipi-csi2", > > + "allwinner,sun6i-a31-mipi-csi2"; > > + reg =3D <0x01cb1000 0x1000>; > > + interrupts =3D ; > > + clocks =3D <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI1_SCLK>; > > + clock-names =3D "bus", "mod"; > > + resets =3D <&ccu RST_BUS_CSI>; > > + status =3D "disabled"; > > + > > + phys =3D <&dphy>; > > + phy-names =3D "dphy"; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + mipi_csi2_in: port@0 { > > + reg =3D <0>; > > + }; > > + > > + mipi_csi2_out: port@1 { > > + reg =3D <1>; > > + > > + mipi_csi2_out_csi0: endpoint { > > + remote-endpoint =3D <&csi0_in_mipi_csi2>; > > + }; > > + }; > > + }; > > + }; > > + > > + dphy: d-phy@1cb2000 { > > + compatible =3D "allwinner,sun6i-a31-mipi-dphy"; > > + reg =3D <0x01cb2000 0x1000>; > > + clocks =3D <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_MIPI_CSI>; > > + clock-names =3D "bus", "mod"; > > + resets =3D <&ccu RST_BUS_CSI>; > > + allwinner,direction =3D "rx"; > > + status =3D "disabled"; > > + #phy-cells =3D <0>; > > + }; > > }; > > }; > >=20 >=20 --=20 Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com --QZVQzP+VTAJydr5U Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEJZpWjZeIetVBefti3cLmz3+fv9EFAmE/AVYACgkQ3cLmz3+f v9EFwAgAlLhO92v/X6G6gs1EKL/Ve3k5WVgSYDcp38cxhVkn9TYIx+u97xSfyDLC P5PABn2O8tERf6e7U1NBmqr64vSzvziaRmeLo6co6sdLEJuNvk4wrp3/9U7+dp/Q 9Pp/tPxadAO4SKID7BW5UKTEzWqzGlsGJf/6p83oKzwWtBCTBXTfK0PjkmESPFy8 kTX1gqi9/Pe0oiWH0PRZJIZzPYDP8PpRNPQNxhPlXivuSnDLFwNAhaSXrMvqOnl2 /Y+tpSRPXTKGPqjIAzRn3G2fTveiHMw0fTLwVgcZqqNIK4dACeQLJYNdSxjTMORZ J1xWZQdStHkESCp9DRxlxV8TLbiItg== =95oz -----END PGP SIGNATURE----- --QZVQzP+VTAJydr5U--