From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5A38A20 for ; Tue, 20 Sep 2022 06:35:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5B27C433C1; Tue, 20 Sep 2022 06:35:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663655734; bh=z4g70PWNS19WDaZZAXAoI1HGOBQ1YJ7dA7waNDxTJ+U=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=l5Twc8sPOZQJX+kvswAylubH6gwPowlY7GN/3Z8oGoS5TZfrtK7a4uw/aA34Hr/0i 1Hvnz9QIGt+0ykQoZKjXYskD2llkqqcGkBnMgOW7C6Tz0T3V9NZqYx/uvuMXhmJrqk JncAZzUVlWHHkplP7W4bIDFqmq3O0/M0PaS9DfI+MnT47jD5MIXSADJo63pevsCPnb Itn0HRwiaLbZdB+t/BnVmlBzNALhmgH0kevAkMp9maNERiBLRJsKYNktFVEsKsI7Mb hQXq+h6kbdfeF+OOhh5BFHVvVTLC3+OOVKYnYr+2/lGB+UvIag5cm2JbcJeIqGhJYj KxdmvuLnuSecA== Date: Tue, 20 Sep 2022 12:05:30 +0530 From: Vinod Koul To: Andre Przywara Cc: Jernej Skrabec , Samuel Holland , Chen-Yu Tsai , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Greg Kroah-Hartman , linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Karl Kurbjun , Icenowy Zheng Subject: Re: [PATCH 2/7] dt-bindings: usb: Add special clock for Allwinner H616 PHY Message-ID: References: <20220911235945.6635-1-andre.przywara@arm.com> <20220911235945.6635-3-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220911235945.6635-3-andre.przywara@arm.com> On 12-09-22, 00:59, Andre Przywara wrote: > The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves > some resources from port 2's PHY and HCI IP. In particular the PMU clock > for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL > register of port 2. To allow each USB port to be controlled > independently of port 2, we need a handle to that particular PMU clock > in the *PHY* node, as the HCI and PHY part might be handled by separate > drivers. > > Add that clock to the requirements of the H616 PHY binding, so that a > PHY driver can apply the quirk in isolation, without requiring help from > port 2's HCI driver. This is phy binding patch and not a usb one, pls fix the subystem name for patch > > Signed-off-by: Andre Przywara > --- > .../phy/allwinner,sun8i-h3-usb-phy.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml > index e288450e0844..3a3168392597 100644 > --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml > @@ -36,18 +36,22 @@ properties: > - const: pmu3 > > clocks: > + minItems: 4 > items: > - description: USB OTG PHY bus clock > - description: USB Host 0 PHY bus clock > - description: USB Host 1 PHY bus clock > - description: USB Host 2 PHY bus clock > + - description: PMU clock for host port 2 > > clock-names: > + minItems: 4 > items: > - const: usb0_phy > - const: usb1_phy > - const: usb2_phy > - const: usb3_phy > + - const: pmu2_clk > > resets: > items: > @@ -98,6 +102,21 @@ required: > > additionalProperties: false > > +if: > + properties: > + compatible: > + contains: > + enum: > + - sun50i-h616-usb-phy > + > +then: > + properties: > + clocks: > + minItems: 5 > + > + clock-names: > + minItems: 5 > + > examples: > - | > #include > -- > 2.35.3 -- ~Vinod