From: Pascal Roeleven <firstname.lastname@example.org> To: Roman Beranek <email@example.com> Cc: "Uwe Kleine-König" <firstname.lastname@example.org>, "Thierry Reding" <email@example.com>, "Emil Lenngren" <firstname.lastname@example.org>, "Lee Jones" <email@example.com>, "Maxime Ripard" <firstname.lastname@example.org>, "Chen-Yu Tsai" <email@example.com>, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com Subject: Re: [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling Date: Mon, 31 May 2021 21:07:54 +0200 [thread overview] Message-ID: <firstname.lastname@example.org> (raw) In-Reply-To: <email@example.com> On 2021-05-31 06:46, Roman Beranek wrote: > As Emil Lenngren has previously shown , actually only 1-2 cycles of > the prescaler-divided clock are necessary to pass before the PWM turns > off, not a full period. > > To avoid having the PWM re-enabled from another thread while asleep, > ctrl_lock spinlock was converted to a mutex so that it can be released > only after the clock gate has finally been turned on. > >  https://linux-sunxi.org/PWM_Controller_Register_Guide > > Roman Beranek (6): > pwm: sun4i: enable clk prior to getting its rate > pwm: sun4i: disable EN bit prior to the delay > pwm: sun4i: replace spinlock with a mutex > pwm: sun4i: simplify calculation of the delay time > pwm: sun4i: shorten the delay to 2 cycles > pwm: sun4i: don't delay if the PWM is already off > > drivers/pwm/pwm-sun4i.c | 56 +++++++++++++++++++---------------------- > 1 file changed, 26 insertions(+), 30 deletions(-) Hi Roman, Thanks for your attempt to fix this. Unfortunately on my A10 device (Topwise A721), the controller still gets stuck in an unrecoverable state after disabling and re-enabling the PWM when it was already on (set in U-Boot), or when enabling it when it was off. In this state, any changes to the period register (using devmem) don't seem to have any effect. It seems to be stuck in the state it was before disabling. The only thing which still works is enabling and disabling. I can't reproduce this behavior manually so I'm not sure what is causing this. Regarding the amount of cycles of sleep; Using a prescaler of 72000 the PWM clock is 3 ms. Although timing tests using devmem seem unreliable (too much overhead?), in U-Boot I need to 'sleep' for at least 7 ms between the commands to make sure the output doesn't sometimes get stuck in the enabled state. So in my case it seems to be at least 3 cycles. I am not sure how reliable this method is. However even if I can get it stuck in the enabled state using a shorter time, it doesn't cause the behavior I mentioned before. I was always able to recover it manually. Increasing the number of cycles to sleep therefore also doesn't solve my problem. Until we can solve that I cannot confirm nor deny if 2 cycles is enough. Regards, Pascal
next prev parent reply other threads:[~2021-05-31 19:24 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-31 4:46 Roman Beranek 2021-05-31 4:46 ` [PATCH 1/6] pwm: sun4i: enable clk prior to getting its rate Roman Beranek 2021-06-07 8:00 ` Uwe Kleine-König 2021-05-31 4:46 ` [PATCH 2/6] pwm: sun4i: disable EN bit prior to the delay Roman Beranek 2021-06-07 8:07 ` Uwe Kleine-König 2021-05-31 4:46 ` [PATCH 3/6] pwm: sun4i: replace spinlock with a mutex Roman Beranek 2021-05-31 4:46 ` [PATCH 4/6] pwm: sun4i: simplify calculation of the delay time Roman Beranek 2021-05-31 4:46 ` [PATCH 5/6] pwm: sun4i: shorten the delay to 2 cycles Roman Beranek 2021-05-31 4:46 ` [PATCH 6/6] pwm: sun4i: don't delay if the PWM is already off Roman Beranek 2021-06-10 13:41 ` Pascal Roeleven 2021-05-31 19:07 ` Pascal Roeleven [this message] 2021-05-31 20:01 ` [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling Emil Lenngren 2021-05-31 20:20 ` Pascal Roeleven 2021-06-08 12:28 ` Pascal Roeleven
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