From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B141C433DF for ; Wed, 5 Aug 2020 05:25:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5252221744 for ; Wed, 5 Aug 2020 05:25:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="kzgoNDou" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725887AbgHEFZk (ORCPT ); Wed, 5 Aug 2020 01:25:40 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:15367 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727035AbgHEFZa (ORCPT ); Wed, 5 Aug 2020 01:25:30 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Aug 2020 22:24:41 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Aug 2020 22:25:30 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Aug 2020 22:25:30 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 5 Aug 2020 05:25:30 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 5 Aug 2020 05:25:30 +0000 Received: from audio.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 04 Aug 2020 22:25:29 -0700 From: Sameer Pujar To: , , , , , CC: , , , , , , , , , , , , , , Sameer Pujar Subject: [PATCH v2 9/9] arm64: tegra: Audio graph sound card for Jetson Nano and TX1 Date: Wed, 5 Aug 2020 10:54:24 +0530 Message-ID: <1596605064-27748-10-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596605064-27748-1-git-send-email-spujar@nvidia.com> References: <1596605064-27748-1-git-send-email-spujar@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596605081; bh=PeBWAGhMOCghx8hYx18FVuqK4MMpd2Y9L+RhDCXfhWg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=kzgoNDou3KTrX3K427xo3xzcGl5v8EfSuIzdcx9pgI4RUSp+wf2w545NexnS2WFg4 UxI4pTLejM8WbnRJzQtLV6QjkRfjECsyoO0QrOzq6elxSEGA2lweK/VBzTu8/x9BT4 31mT7Od1NLKutolVbaOGtlrv1MwXsPlg04ivw/Kac3lcdRewafBXJFaH9OWxeH5AY6 XynjPFEQDahV+axbi5n6dyZsaRmcNJs5AkyGmuk6U4QkJW1xZY10kymqf4yE6u4+w9 sL97VPGqD6UQjy7xI1TwonhnOe6Nm6jjgVlBlMNEafoQ1cy2HKep+5njUS4OunZFMr IhbjePRbQWq2A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable support for audio-graph based sound card on Jetson-Nano and Jetson-TX1. Depending on the platform, required I/O interfaces are enabled. * Jetson-Nano: Enable I2S3, I2S4, DMIC1 and DMIC2. * Jetson-TX1: Enable all I2S and DMIC interfaces. Signed-off-by: Sameer Pujar --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 217 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 122 ++++++++++++ 2 files changed, 339 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 56adf28..0eefad7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -3,6 +3,7 @@ #include "tegra210-p2180.dtsi" #include "tegra210-p2597.dtsi" +#include "tegra210-audio-graph.dtsi" / { model = "NVIDIA Jetson TX1 Developer Kit"; @@ -126,4 +127,220 @@ status = "okay"; }; }; + + tegra_sound { + status = "okay"; + + dais = /* FE */ + <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, + <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, + <&admaif10_port>, + /* Router */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, + <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>, + <&xbar_dmic2_port>, <&xbar_dmic3_port>, + /* I/O DAP Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, + <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; + + label = "jetson-tx1-ape"; + }; +}; + +&tegra_admaif { + status = "okay"; +}; + +&tegra_ahub { + status = "okay"; + + ports { + xbar_i2s1_port: port@a { + reg = <0xa>; + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + xbar_i2s2_port: port@b { + reg = <0xb>; + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; + }; + }; + xbar_i2s3_port: port@c { + reg = <0xc>; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + xbar_i2s4_port: port@d { + reg = <0xd>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + xbar_i2s5_port: port@e { + reg = <0xe>; + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + xbar_dmic1_port: port@f { + reg = <0xf>; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + xbar_dmic2_port: port@10 { + reg = <0x10>; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + xbar_dmic3_port: port@11 { + reg = <0x11>; + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; + }; + }; + }; +}; + +&tegra_i2s1 { + status = "okay"; + + port@0 { + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + + i2s1_port: port@1 { + i2s1_dap: endpoint { + dai-format = "i2s"; + + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_i2s2 { + status = "okay"; + + port@0 { + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; + }; + + i2s2_port: port@1 { + i2s2_dap: endpoint { + dai-format = "i2s"; + + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_i2s3 { + status = "okay"; + + port@0 { + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_i2s4 { + status = "okay"; + + port@0 { + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + + i2s4_port: port@1 { + i2s4_dap: endpoint { + dai-format = "i2s"; + + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_i2s5 { + status = "okay"; + + port@0 { + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + + i2s5_port: port@1 { + i2s5_dap: endpoint { + dai-format = "i2s"; + + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_dmic1 { + status = "okay"; + + port@0 { + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + dmic1_dap: endpoint { + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_dmic2 { + status = "okay"; + + port@0 { + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + dmic2_dap: endpoint { + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_dmic3 { + status = "okay"; + + port@0 { + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + + dmic3_port: port@1 { + dmic3_dap: endpoint { + /* Placeholder for external Codec */ + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 0dd3d02..dc6a1d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -6,6 +6,7 @@ #include #include "tegra210.dtsi" +#include "tegra210-audio-graph.dtsi" / { model = "NVIDIA Jetson Nano Developer Kit"; @@ -855,4 +856,125 @@ status = "okay"; }; }; + + tegra_sound { + status = "okay"; + + dais = /* FE */ + <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, + <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, + <&admaif10_port>, + /* Router */ + <&xbar_i2s3_port>, <&xbar_i2s4_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, + /* I/O DAP Ports */ + <&i2s3_port>, <&i2s4_port>, + <&dmic1_port>, <&dmic2_port>; + + label = "jetson-nano-ape"; + }; +}; + +&tegra_admaif { + status = "okay"; +}; + +&tegra_ahub { + status = "okay"; + + ports { + xbar_i2s3_port: port@c { + reg = <0xc>; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + xbar_i2s4_port: port@d { + reg = <0xd>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + xbar_dmic1_port: port@f { + reg = <0xf>; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + xbar_dmic2_port: port@10 { + reg = <0x10>; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + }; +}; + +&tegra_i2s3 { + status = "okay"; + + port@0 { + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_i2s4 { + status = "okay"; + + port@0 { + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + + i2s4_port: port@1 { + i2s4_dap: endpoint@0 { + dai-format = "i2s"; + + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_dmic1 { + status = "okay"; + + port@0 { + dmic1_cif_ep: endpoint@0 { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + dmic1_dap: endpoint@0 { + /* Placeholder for external Codec */ + }; + }; +}; + +&tegra_dmic2 { + status = "okay"; + + port@0 { + dmic2_cif_ep: endpoint@0 { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + dmic2_dap: endpoint@0 { + /* Placeholder for external Codec */ + }; + }; }; -- 2.7.4