On Wed, Sep 09, 2020 at 04:10:27PM +0800, JC Kuo wrote:
> PLLE has a hardware power sequencer logic which is a state machine
> that can power on/off PLLE without any software intervention. The
> sequencer has two inputs, one from XUSB UPHY PLL and the other from
> SATA UPHY PLL. PLLE provides reference clock to XUSB and SATA UPHY
> PLLs. When both of the downstream PLLs are powered-off, PLLE hardware
> power sequencer will automatically power off PLLE for power saving.
> 
> XUSB and SATA UPHY PLLs also have their own hardware power sequencer
> logic. XUSB UPHY PLL is shared between XUSB SuperSpeed ports and PCIE
> controllers. The XUSB UPHY PLL hardware power sequencer has inputs
> from XUSB and PCIE. When all of the XUSB SuperSpeed ports and PCIE
> controllers are in low power state, XUSB UPHY PLL hardware power
> sequencer automatically power off PLL and flags idle to PLLE hardware
> power sequencer. Similar applies to SATA UPHY PLL.
> 
> PLLE hardware power sequencer has to be enabled after both downstream
> sequencers are enabled.
> 
> This commit adds two helper functions:
> 1. tegra210_plle_hw_sequence_start() for XUSB PADCTL driver to enable
>    PLLE hardware sequencer at proper time.
> 
> 2. tegra210_plle_hw_sequence_is_enabled() for XUSB PADCTL driver to
>    check whether PLLE hardware sequencer has been enabled or not.
> 
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---
> v3:
>    rename 'val' with 'value
> 
>  drivers/clk/tegra/clk-tegra210.c | 51 ++++++++++++++++++++++++++++++++
>  include/linux/clk/tegra.h        |  2 ++
>  2 files changed, 53 insertions(+)

Acked-by: Thierry Reding <treding@nvidia.com>