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From: Thierry Reding <thierry.reding@gmail.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Dmitry Osipenko <digetx@gmail.com>,
	Sowjanya Komatineni <skomatineni@nvidia.com>,
	Venkat Reddy Talla <vreddytalla@nvidia.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	kernel-team@android.com
Subject: Re: [PATCH 0/3] soc/tegra: Prevent the PMC driver from corrupting interrupt routing
Date: Mon, 5 Oct 2020 13:22:17 +0200	[thread overview]
Message-ID: <20201005112217.GR425362@ulmo> (raw)
In-Reply-To: <20201005111443.1390096-1-maz@kernel.org>

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On Mon, Oct 05, 2020 at 12:14:40PM +0100, Marc Zyngier wrote:
> Jon recently reported that one of the Tegra systems (Jetson TX2, aka
> tegra186) stopped booting with the introduction of the "IPI as IRQs"
> series. After a few weeks of head scratching and complete puzzlement,
> I obtained a board and started looking at what was happening.
> 
> The interrupt hierarchy looks like this:
> 
> 	[DEVICE] -A-> [PMC] -B-> [GIC]
> 
> which seems simple enough. However, not all the devices attached to
> the PMC follow this hierarchy, and in some cases, the 'B' link isn't
> present in the HW. In other cases, neither 'A' nor 'B' are present.
> And yet the PMC driver creates such linkages using random hwirq values
> for the non-existent links, potentially overriding existing mappings
> in the process. "What could possibly go wrong?"

Yes, that would've been my fault. It seemed like the right thing to do
at the time, but the way you describe it makes it obvious that it was
not. I can't say I understand why this would've worked prior to the
rework that made this surface, though.

> It turns out that for the 'B' link, the PMC driver uses hwirq 0, which
> is SGI0 for the GIC, and used as the rescheduling IPI. Obviously, this
> doesn't go very well, nor very far, as the IPI gets routed to random
> drivers. Also, as the handling flow has been overridden, this
> interrupt never gets deactivated and can't fire anymore. Yes, this is
> bad.
> 
> The 'A' link is less problematic, but the hwirq value is still out of
> the irqdomain range, and gets remapped every time a new 'A'-less
> driver comes up.
> 
> Instead, let's trim the unused hierarchy levels as needed. This
> requires some checks in the upper levels of the hierarchy as we now
> have optional levels, but this looks a lot saner than what we
> currently have. With this, tegra186 is back booting on -next.
> 
> I haven't tested any wake-up stuff, nor any other nvidia system (this
> is the only one I have). If people agree to these changes, I can take
> them via the irqchip tree so that they make it into the next merge
> window.

Yeah, it sounds like this needs to go in ideally before the rework that
caused this to surface in order to preserve bisectibility. But if it
goes in afterwards that's probably fine as well.

Let Jon and myself do a bit of testing with this to verify that the wake
up paths are still working.

Thierry

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  parent reply	other threads:[~2020-10-05 11:22 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-05 11:14 [PATCH 0/3] soc/tegra: Prevent the PMC driver from corrupting interrupt routing Marc Zyngier
2020-10-05 11:14 ` [PATCH 1/3] gpio: tegra186: Allow optional irq parent callbacks Marc Zyngier
2020-10-05 11:14 ` [PATCH 2/3] soc/tegra: pmc: " Marc Zyngier
2020-10-05 11:27   ` Thierry Reding
2020-10-05 12:59     ` Marc Zyngier
2020-10-05 11:14 ` [PATCH 3/3] soc/tegra: pmc: Don't create fake interrupt hierarchy levels Marc Zyngier
2020-10-05 11:33   ` Thierry Reding
2020-10-05 13:10     ` Marc Zyngier
2020-10-05 11:22 ` Thierry Reding [this message]
2020-10-05 13:06   ` [PATCH 0/3] soc/tegra: Prevent the PMC driver from corrupting interrupt routing Marc Zyngier
2020-10-05 15:45     ` Thierry Reding
2020-10-05 18:23       ` Jon Hunter

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