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From: Thierry Reding <thierry.reding@gmail.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: krzk@kernel.org, robh+dt@kernel.org, jonathanh@nvidia.com,
	linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/5] memory: tegra: Correct la.reg address of seswr
Date: Fri, 9 Oct 2020 14:11:41 +0200	[thread overview]
Message-ID: <20201009121141.GA458338@ulmo> (raw)
In-Reply-To: <20201008003746.25659-2-nicoleotsuka@gmail.com>

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On Wed, Oct 07, 2020 at 05:37:42PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
> [23:16] of register at address 0x3e0 with a reset value of 0x80
> at register 0x3e0, while bit-1 of register 0xb98 is for enable
> bit of seswr. So this patch fixes it.
> 
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
>  drivers/memory/tegra/tegra210.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index 7fb8b5438bf4..088814279616 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
>  			.bit = 1,
>  		},
>  		.la = {
> -			.reg = 0xb98,
> +			.reg = 0x3e0,
>  			.shift = 16,
>  			.mask = 0xff,
>  			.def = 0x80,

Heh, indeed. Look like I copied the reg offset from the .smmu.reg by
mistake.

Acked-by: Thierry Reding <treding@nvidia.com>

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  reply	other threads:[~2020-10-09 12:11 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-08  0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
2020-10-08  0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
2020-10-09 12:11   ` Thierry Reding [this message]
2020-10-26 20:14   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
2020-10-09 12:14   ` Thierry Reding
2020-10-26 20:15   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
2020-10-08 10:32   ` Krzysztof Kozlowski
2020-10-08 20:26     ` Nicolin Chen
2020-10-12 16:43       ` Krzysztof Kozlowski
2020-10-12 18:57         ` Nicolin Chen
2020-10-09 12:15   ` Thierry Reding
2020-10-26 20:17   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
2020-10-09 12:21   ` Thierry Reding
2020-10-09 15:52     ` Nicolin Chen
2020-10-26 20:17       ` Krzysztof Kozlowski
2020-10-27 12:55         ` Thierry Reding
2020-10-27 23:31           ` Nicolin Chen
2020-10-27 19:54   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
2020-10-27 13:01   ` Thierry Reding
2020-10-27 23:37     ` Nicolin Chen
2020-11-20 16:27   ` Thierry Reding
2020-11-22 11:07   ` Krzysztof Kozlowski
2020-10-08 10:29 ` [PATCH 0/5] memory: tegra: Fix client list and add swgroups Krzysztof Kozlowski
2020-10-08 20:27   ` Nicolin Chen

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