* [PATCH 0/5] memory: tegra: Fix client list and add swgroups
@ 2020-10-08 0:37 Nicolin Chen
2020-10-08 0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
` (5 more replies)
0 siblings, 6 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 0:37 UTC (permalink / raw)
To: krzk, thierry.reding, robh+dt
Cc: jonathanh, linux-tegra, devicetree, linux-kernel
This series has two fixes of tegra210_mc_clients, and three
changes to add missing swgroups, according to Tegra X1 TRM.
Nicolin Chen (5):
memory: tegra: Correct la.reg address of seswr
memory: tegra: Correct tegra210_mc_clients def values
memory: tegra: Sort tegra210_swgroups by reg address
dt-bindings: memory: tegra: Add missing swgroups
memory: tegra: Complete tegra210_swgroups
drivers/memory/tegra/tegra210.c | 60 ++++++++++++++----------
include/dt-bindings/memory/tegra210-mc.h | 10 ++++
2 files changed, 45 insertions(+), 25 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/5] memory: tegra: Correct la.reg address of seswr
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
@ 2020-10-08 0:37 ` Nicolin Chen
2020-10-09 12:11 ` Thierry Reding
2020-10-26 20:14 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
` (4 subsequent siblings)
5 siblings, 2 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 0:37 UTC (permalink / raw)
To: krzk, thierry.reding, robh+dt
Cc: jonathanh, linux-tegra, devicetree, linux-kernel
According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
[23:16] of register at address 0x3e0 with a reset value of 0x80
at register 0x3e0, while bit-1 of register 0xb98 is for enable
bit of seswr. So this patch fixes it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
drivers/memory/tegra/tegra210.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 7fb8b5438bf4..088814279616 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.bit = 1,
},
.la = {
- .reg = 0xb98,
+ .reg = 0x3e0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
2020-10-08 0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
@ 2020-10-08 0:37 ` Nicolin Chen
2020-10-09 12:14 ` Thierry Reding
2020-10-26 20:15 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
` (3 subsequent siblings)
5 siblings, 2 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 0:37 UTC (permalink / raw)
To: krzk, thierry.reding, robh+dt
Cc: jonathanh, linux-tegra, devicetree, linux-kernel
Some def values are mismatched with Tegra X1 TRM, probably because
being copied from tegra124.c file. So this patch fixes them.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
drivers/memory/tegra/tegra210.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 088814279616..e8a7d266802c 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -24,7 +24,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2e8,
.shift = 0,
.mask = 0xff,
- .def = 0xc2,
+ .def = 0x1e,
},
}, {
.id = 0x02,
@@ -38,7 +38,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2f4,
.shift = 0,
.mask = 0xff,
- .def = 0xc6,
+ .def = 0x1e,
},
}, {
.id = 0x03,
@@ -52,7 +52,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2e8,
.shift = 16,
.mask = 0xff,
- .def = 0x50,
+ .def = 0x1e,
},
}, {
.id = 0x04,
@@ -66,7 +66,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2f4,
.shift = 16,
.mask = 0xff,
- .def = 0x50,
+ .def = 0x1e,
},
}, {
.id = 0x05,
@@ -80,7 +80,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2ec,
.shift = 0,
.mask = 0xff,
- .def = 0x50,
+ .def = 0x1e,
},
}, {
.id = 0x06,
@@ -94,7 +94,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2f8,
.shift = 0,
.mask = 0xff,
- .def = 0x50,
+ .def = 0x1e,
},
}, {
.id = 0x0e,
@@ -108,7 +108,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2e0,
.shift = 0,
.mask = 0xff,
- .def = 0x13,
+ .def = 0x2e,
},
}, {
.id = 0x0f,
@@ -136,7 +136,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2f0,
.shift = 0,
.mask = 0xff,
- .def = 0x50,
+ .def = 0x1e,
},
}, {
.id = 0x11,
@@ -150,7 +150,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2fc,
.shift = 0,
.mask = 0xff,
- .def = 0x50,
+ .def = 0x1e,
},
}, {
.id = 0x15,
@@ -380,7 +380,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x350,
.shift = 16,
.mask = 0xff,
- .def = 0x65,
+ .def = 0x80,
},
}, {
.id = 0x44,
@@ -620,7 +620,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x2f0,
.shift = 16,
.mask = 0xff,
- .def = 0x50,
+ .def = 0x1e,
},
}, {
.id = 0x60,
@@ -648,7 +648,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x3bc,
.shift = 0,
.mask = 0xff,
- .def = 0x49,
+ .def = 0x5a,
},
}, {
.id = 0x62,
@@ -676,7 +676,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x3c4,
.shift = 0,
.mask = 0xff,
- .def = 0x49,
+ .def = 0x5a,
},
}, {
.id = 0x64,
@@ -956,7 +956,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.reg = 0x3ec,
.shift = 16,
.mask = 0xff,
- .def = 0xff,
+ .def = 0x80,
},
}, {
.id = 0x86,
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
2020-10-08 0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
2020-10-08 0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
@ 2020-10-08 0:37 ` Nicolin Chen
2020-10-08 10:32 ` Krzysztof Kozlowski
` (2 more replies)
2020-10-08 0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
` (2 subsequent siblings)
5 siblings, 3 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 0:37 UTC (permalink / raw)
To: krzk, thierry.reding, robh+dt
Cc: jonathanh, linux-tegra, devicetree, linux-kernel
This is a cleanup change to prepare for new swgroups.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index e8a7d266802c..b400802c9f14 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
};
static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
- { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
- { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
- { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
+ { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
+ { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
+ { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
+ { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
- { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
+ { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
+ { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
- { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
- { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
- { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
+ { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
- { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
- { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
+ { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
+ { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
{ .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
{ .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
- { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
{ .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
+ { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
{ .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
{ .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
` (2 preceding siblings ...)
2020-10-08 0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
@ 2020-10-08 0:37 ` Nicolin Chen
2020-10-09 12:21 ` Thierry Reding
2020-10-27 19:54 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
2020-10-08 10:29 ` [PATCH 0/5] memory: tegra: Fix client list and add swgroups Krzysztof Kozlowski
5 siblings, 2 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 0:37 UTC (permalink / raw)
To: krzk, thierry.reding, robh+dt
Cc: jonathanh, linux-tegra, devicetree, linux-kernel
According to Tegra X1 TRM, there are missing swgroups in the
tegra210_swgroups list. So this patch adds them in bindings.
Note that the TEGRA_SWGROUP_GPU (in list) should be actually
TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
TEGRA_SWGROUP_GPU (in list) as it is.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
index c226cba9e077..f9fcb18a6d9b 100644
--- a/include/dt-bindings/memory/tegra210-mc.h
+++ b/include/dt-bindings/memory/tegra210-mc.h
@@ -33,6 +33,16 @@
#define TEGRA_SWGROUP_AXIAP 28
#define TEGRA_SWGROUP_ETR 29
#define TEGRA_SWGROUP_TSECB 30
+#define TEGRA_SWGROUP_NV 31
+#define TEGRA_SWGROUP_NV2 32
+#define TEGRA_SWGROUP_PPCS1 33
+#define TEGRA_SWGROUP_DC1 34
+#define TEGRA_SWGROUP_PPCS2 35
+#define TEGRA_SWGROUP_HC1 36
+#define TEGRA_SWGROUP_SE1 37
+#define TEGRA_SWGROUP_TSEC1 38
+#define TEGRA_SWGROUP_TSECB1 39
+#define TEGRA_SWGROUP_NVDEC1 40
#define TEGRA210_MC_RESET_AFI 0
#define TEGRA210_MC_RESET_AVPC 1
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 5/5] memory: tegra: Complete tegra210_swgroups
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
` (3 preceding siblings ...)
2020-10-08 0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
@ 2020-10-08 0:37 ` Nicolin Chen
2020-10-27 13:01 ` Thierry Reding
` (2 more replies)
2020-10-08 10:29 ` [PATCH 0/5] memory: tegra: Fix client list and add swgroups Krzysztof Kozlowski
5 siblings, 3 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 0:37 UTC (permalink / raw)
To: krzk, thierry.reding, robh+dt
Cc: jonathanh, linux-tegra, devicetree, linux-kernel
According to Tegra X1 TRM, there are missing swgroups in the
tegra210_swgroups list. So this patch adds them to the list.
Note that the TEGRA_SWGROUP_GPU (in list) should be actually
TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
TEGRA_SWGROUP_GPU (in list) as it is.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
drivers/memory/tegra/tegra210.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index b400802c9f14..b3bbc5a05ba1 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
+ { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
+ { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
@@ -1036,19 +1038,27 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
+ { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 },
+ { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 },
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
{ .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
{ .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
+ { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 },
{ .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
{ .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
{ .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
{ .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
+ { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 },
+ { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 },
{ .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
{ .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
+ { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 },
+ { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc },
+ { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 },
};
static const unsigned int tegra210_group_display[] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 0/5] memory: tegra: Fix client list and add swgroups
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
` (4 preceding siblings ...)
2020-10-08 0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
@ 2020-10-08 10:29 ` Krzysztof Kozlowski
2020-10-08 20:27 ` Nicolin Chen
5 siblings, 1 reply; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-08 10:29 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Thu, 8 Oct 2020 at 02:44, Nicolin Chen <nicoleotsuka@gmail.com> wrote:
>
> This series has two fixes of tegra210_mc_clients, and three
> changes to add missing swgroups, according to Tegra X1 TRM.
>
> Nicolin Chen (5):
> memory: tegra: Correct la.reg address of seswr
> memory: tegra: Correct tegra210_mc_clients def values
> memory: tegra: Sort tegra210_swgroups by reg address
> dt-bindings: memory: tegra: Add missing swgroups
> memory: tegra: Complete tegra210_swgroups
Hi,
It's too late in the cycle for another pull request so this will wait
for merge window to finish.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
2020-10-08 0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
@ 2020-10-08 10:32 ` Krzysztof Kozlowski
2020-10-08 20:26 ` Nicolin Chen
2020-10-09 12:15 ` Thierry Reding
2020-10-26 20:17 ` Krzysztof Kozlowski
2 siblings, 1 reply; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-08 10:32 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> This is a cleanup change to prepare for new swgroups.
What type of cleanup? Any functional change?
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index e8a7d266802c..b400802c9f14 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
> };
>
> static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
> { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
> - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
> + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
> { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
> - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
> { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
> - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
I must say I cannot find the order. By name - not. By swgroup name -
not. By register - not.
What is the order then?
Best regards,
Krzysztof
> - { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
> + { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
> { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
> { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
> { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
> - { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> - { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> + { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> + { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
> { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
> { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
> - { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
> { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
> + { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
> { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
> { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
> { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
2020-10-08 10:32 ` Krzysztof Kozlowski
@ 2020-10-08 20:26 ` Nicolin Chen
2020-10-12 16:43 ` Krzysztof Kozlowski
0 siblings, 1 reply; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 20:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
Hi Krzysztof,
On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote:
> On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> > This is a cleanup change to prepare for new swgroups.
>
> What type of cleanup? Any functional change?
It's to sort the swgroup list by reg address as I mentioned in
the subject. Perhaps I should have put in commit message also.
> >
> > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > ---
> > drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> > index e8a7d266802c..b400802c9f14 100644
> > --- a/drivers/memory/tegra/tegra210.c
> > +++ b/drivers/memory/tegra/tegra210.c
> > @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
> > };
> >
> > static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> > - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> > - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> > { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
> > { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
> > - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> > + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
> > + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
> > { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
> > + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> > + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> > { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
> > { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
> > - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> > + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
> > + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
> > { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
> > { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
> > - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
> > - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
> > { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
>
> I must say I cannot find the order. By name - not. By swgroup name -
> not. By register - not.
>
> What is the order then?
It's by "reg" as I mentioned in the commit subject. Probably
it's not that obvious by looking at the change itself :-/
Its following change of adding new swgroups would be easier
to insert by following the same order of "reg" addresses.
Thanks
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/5] memory: tegra: Fix client list and add swgroups
2020-10-08 10:29 ` [PATCH 0/5] memory: tegra: Fix client list and add swgroups Krzysztof Kozlowski
@ 2020-10-08 20:27 ` Nicolin Chen
0 siblings, 0 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-08 20:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
Hi Krzysztof,
On Thu, Oct 08, 2020 at 12:29:06PM +0200, Krzysztof Kozlowski wrote:
> On Thu, 8 Oct 2020 at 02:44, Nicolin Chen <nicoleotsuka@gmail.com> wrote:
> >
> > This series has two fixes of tegra210_mc_clients, and three
> > changes to add missing swgroups, according to Tegra X1 TRM.
> >
> > Nicolin Chen (5):
> > memory: tegra: Correct la.reg address of seswr
> > memory: tegra: Correct tegra210_mc_clients def values
> > memory: tegra: Sort tegra210_swgroups by reg address
> > dt-bindings: memory: tegra: Add missing swgroups
> > memory: tegra: Complete tegra210_swgroups
>
> Hi,
>
> It's too late in the cycle for another pull request so this will wait
> for merge window to finish.
I see. Thanks for telling me this!
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/5] memory: tegra: Correct la.reg address of seswr
2020-10-08 0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
@ 2020-10-09 12:11 ` Thierry Reding
2020-10-26 20:14 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Thierry Reding @ 2020-10-09 12:11 UTC (permalink / raw)
To: Nicolin Chen
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
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On Wed, Oct 07, 2020 at 05:37:42PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
> [23:16] of register at address 0x3e0 with a reset value of 0x80
> at register 0x3e0, while bit-1 of register 0xb98 is for enable
> bit of seswr. So this patch fixes it.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index 7fb8b5438bf4..088814279616 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
> .bit = 1,
> },
> .la = {
> - .reg = 0xb98,
> + .reg = 0x3e0,
> .shift = 16,
> .mask = 0xff,
> .def = 0x80,
Heh, indeed. Look like I copied the reg offset from the .smmu.reg by
mistake.
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values
2020-10-08 0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
@ 2020-10-09 12:14 ` Thierry Reding
2020-10-26 20:15 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Thierry Reding @ 2020-10-09 12:14 UTC (permalink / raw)
To: Nicolin Chen
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 452 bytes --]
On Wed, Oct 07, 2020 at 05:37:43PM -0700, Nicolin Chen wrote:
> Some def values are mismatched with Tegra X1 TRM, probably because
> being copied from tegra124.c file. So this patch fixes them.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
Looks good:
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
2020-10-08 0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
2020-10-08 10:32 ` Krzysztof Kozlowski
@ 2020-10-09 12:15 ` Thierry Reding
2020-10-26 20:17 ` Krzysztof Kozlowski
2 siblings, 0 replies; 28+ messages in thread
From: Thierry Reding @ 2020-10-09 12:15 UTC (permalink / raw)
To: Nicolin Chen
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 352 bytes --]
On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> This is a cleanup change to prepare for new swgroups.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
2020-10-08 0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
@ 2020-10-09 12:21 ` Thierry Reding
2020-10-09 15:52 ` Nicolin Chen
2020-10-27 19:54 ` Krzysztof Kozlowski
1 sibling, 1 reply; 28+ messages in thread
From: Thierry Reding @ 2020-10-09 12:21 UTC (permalink / raw)
To: Nicolin Chen
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1626 bytes --]
On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them in bindings.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> index c226cba9e077..f9fcb18a6d9b 100644
> --- a/include/dt-bindings/memory/tegra210-mc.h
> +++ b/include/dt-bindings/memory/tegra210-mc.h
> @@ -33,6 +33,16 @@
> #define TEGRA_SWGROUP_AXIAP 28
> #define TEGRA_SWGROUP_ETR 29
> #define TEGRA_SWGROUP_TSECB 30
> +#define TEGRA_SWGROUP_NV 31
> +#define TEGRA_SWGROUP_NV2 32
> +#define TEGRA_SWGROUP_PPCS1 33
> +#define TEGRA_SWGROUP_DC1 34
> +#define TEGRA_SWGROUP_PPCS2 35
> +#define TEGRA_SWGROUP_HC1 36
> +#define TEGRA_SWGROUP_SE1 37
> +#define TEGRA_SWGROUP_TSEC1 38
> +#define TEGRA_SWGROUP_TSECB1 39
> +#define TEGRA_SWGROUP_NVDEC1 40
I'm not sure this is right. The existing list is based on "Table 4:
Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
none of these new swgroups seem to be present in that table.
Where exactly did you get those from?
Thierry
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
2020-10-09 12:21 ` Thierry Reding
@ 2020-10-09 15:52 ` Nicolin Chen
2020-10-26 20:17 ` Krzysztof Kozlowski
0 siblings, 1 reply; 28+ messages in thread
From: Nicolin Chen @ 2020-10-09 15:52 UTC (permalink / raw)
To: Thierry Reding
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > According to Tegra X1 TRM, there are missing swgroups in the
> > tegra210_swgroups list. So this patch adds them in bindings.
> >
> > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > TEGRA_SWGROUP_GPU (in list) as it is.
> >
> > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > ---
> > include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > index c226cba9e077..f9fcb18a6d9b 100644
> > --- a/include/dt-bindings/memory/tegra210-mc.h
> > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > @@ -33,6 +33,16 @@
> > #define TEGRA_SWGROUP_AXIAP 28
> > #define TEGRA_SWGROUP_ETR 29
> > #define TEGRA_SWGROUP_TSECB 30
> > +#define TEGRA_SWGROUP_NV 31
> > +#define TEGRA_SWGROUP_NV2 32
> > +#define TEGRA_SWGROUP_PPCS1 33
> > +#define TEGRA_SWGROUP_DC1 34
> > +#define TEGRA_SWGROUP_PPCS2 35
> > +#define TEGRA_SWGROUP_HC1 36
> > +#define TEGRA_SWGROUP_SE1 37
> > +#define TEGRA_SWGROUP_TSEC1 38
> > +#define TEGRA_SWGROUP_TSECB1 39
> > +#define TEGRA_SWGROUP_NVDEC1 40
>
> I'm not sure this is right. The existing list is based on "Table 4:
> Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> none of these new swgroups seem to be present in that table.
I went through all the MC_SMMU_XX_ASID_0 registers. All of
them have their own ASID registers that I added in PATCH-5.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
2020-10-08 20:26 ` Nicolin Chen
@ 2020-10-12 16:43 ` Krzysztof Kozlowski
2020-10-12 18:57 ` Nicolin Chen
0 siblings, 1 reply; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-12 16:43 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Thu, Oct 08, 2020 at 01:26:16PM -0700, Nicolin Chen wrote:
> Hi Krzysztof,
>
> On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote:
> > On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> > > This is a cleanup change to prepare for new swgroups.
> >
> > What type of cleanup? Any functional change?
>
> It's to sort the swgroup list by reg address as I mentioned in
> the subject. Perhaps I should have put in commit message also.
Indeed it is sorted by regs, I missed some numbers... looks good. I can
adjust the commit msg so no need for resend.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
2020-10-12 16:43 ` Krzysztof Kozlowski
@ 2020-10-12 18:57 ` Nicolin Chen
0 siblings, 0 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-12 18:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Mon, Oct 12, 2020 at 06:43:40PM +0200, Krzysztof Kozlowski wrote:
> On Thu, Oct 08, 2020 at 01:26:16PM -0700, Nicolin Chen wrote:
> > Hi Krzysztof,
> >
> > On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote:
> > > On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> > > > This is a cleanup change to prepare for new swgroups.
> > >
> > > What type of cleanup? Any functional change?
> >
> > It's to sort the swgroup list by reg address as I mentioned in
> > the subject. Perhaps I should have put in commit message also.
>
> Indeed it is sorted by regs, I missed some numbers... looks good. I can
> adjust the commit msg so no need for resend.
Thank you!
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/5] memory: tegra: Correct la.reg address of seswr
2020-10-08 0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
2020-10-09 12:11 ` Thierry Reding
@ 2020-10-26 20:14 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-26 20:14 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Wed, Oct 07, 2020 at 05:37:42PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
> [23:16] of register at address 0x3e0 with a reset value of 0x80
> at register 0x3e0, while bit-1 of register 0xb98 is for enable
> bit of seswr.
> So this patch fixes it.
Either use the imperative form ("Fix foo bar register address") or just
skip the last sentence as it is quite obvious.
https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L151
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values
2020-10-08 0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
2020-10-09 12:14 ` Thierry Reding
@ 2020-10-26 20:15 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-26 20:15 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Wed, Oct 07, 2020 at 05:37:43PM -0700, Nicolin Chen wrote:
> Some def values are mismatched with Tegra X1 TRM, probably because
> being copied from tegra124.c file. So this patch fixes them.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address
2020-10-08 0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
2020-10-08 10:32 ` Krzysztof Kozlowski
2020-10-09 12:15 ` Thierry Reding
@ 2020-10-26 20:17 ` Krzysztof Kozlowski
2 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-26 20:17 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote:
> This is a cleanup change to prepare for new swgroups.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
Thanks, applied with adjusted commit msg (use imperative mode, so
"Cleanup list of ...").
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
2020-10-09 15:52 ` Nicolin Chen
@ 2020-10-26 20:17 ` Krzysztof Kozlowski
2020-10-27 12:55 ` Thierry Reding
0 siblings, 1 reply; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-26 20:17 UTC (permalink / raw)
To: Nicolin Chen
Cc: Thierry Reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Fri, Oct 09, 2020 at 08:52:18AM -0700, Nicolin Chen wrote:
> On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> > On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > > According to Tegra X1 TRM, there are missing swgroups in the
> > > tegra210_swgroups list. So this patch adds them in bindings.
> > >
> > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > > TEGRA_SWGROUP_GPU (in list) as it is.
> > >
> > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > > ---
> > > include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > > index c226cba9e077..f9fcb18a6d9b 100644
> > > --- a/include/dt-bindings/memory/tegra210-mc.h
> > > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > > @@ -33,6 +33,16 @@
> > > #define TEGRA_SWGROUP_AXIAP 28
> > > #define TEGRA_SWGROUP_ETR 29
> > > #define TEGRA_SWGROUP_TSECB 30
> > > +#define TEGRA_SWGROUP_NV 31
> > > +#define TEGRA_SWGROUP_NV2 32
> > > +#define TEGRA_SWGROUP_PPCS1 33
> > > +#define TEGRA_SWGROUP_DC1 34
> > > +#define TEGRA_SWGROUP_PPCS2 35
> > > +#define TEGRA_SWGROUP_HC1 36
> > > +#define TEGRA_SWGROUP_SE1 37
> > > +#define TEGRA_SWGROUP_TSEC1 38
> > > +#define TEGRA_SWGROUP_TSECB1 39
> > > +#define TEGRA_SWGROUP_NVDEC1 40
> >
> > I'm not sure this is right. The existing list is based on "Table 4:
> > Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> > none of these new swgroups seem to be present in that table.
>
> I went through all the MC_SMMU_XX_ASID_0 registers. All of
> them have their own ASID registers that I added in PATCH-5.
Thierry,
Any follow ups on this topic? Does it require a fix or looks correct?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
2020-10-26 20:17 ` Krzysztof Kozlowski
@ 2020-10-27 12:55 ` Thierry Reding
2020-10-27 23:31 ` Nicolin Chen
0 siblings, 1 reply; 28+ messages in thread
From: Thierry Reding @ 2020-10-27 12:55 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Nicolin Chen, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2747 bytes --]
On Mon, Oct 26, 2020 at 09:17:58PM +0100, Krzysztof Kozlowski wrote:
> On Fri, Oct 09, 2020 at 08:52:18AM -0700, Nicolin Chen wrote:
> > On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> > > On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > > > According to Tegra X1 TRM, there are missing swgroups in the
> > > > tegra210_swgroups list. So this patch adds them in bindings.
> > > >
> > > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > > > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > > > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > > > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > > > TEGRA_SWGROUP_GPU (in list) as it is.
> > > >
> > > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > > > ---
> > > > include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> > > > 1 file changed, 10 insertions(+)
> > > >
> > > > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > > > index c226cba9e077..f9fcb18a6d9b 100644
> > > > --- a/include/dt-bindings/memory/tegra210-mc.h
> > > > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > > > @@ -33,6 +33,16 @@
> > > > #define TEGRA_SWGROUP_AXIAP 28
> > > > #define TEGRA_SWGROUP_ETR 29
> > > > #define TEGRA_SWGROUP_TSECB 30
> > > > +#define TEGRA_SWGROUP_NV 31
> > > > +#define TEGRA_SWGROUP_NV2 32
> > > > +#define TEGRA_SWGROUP_PPCS1 33
> > > > +#define TEGRA_SWGROUP_DC1 34
> > > > +#define TEGRA_SWGROUP_PPCS2 35
> > > > +#define TEGRA_SWGROUP_HC1 36
> > > > +#define TEGRA_SWGROUP_SE1 37
> > > > +#define TEGRA_SWGROUP_TSEC1 38
> > > > +#define TEGRA_SWGROUP_TSECB1 39
> > > > +#define TEGRA_SWGROUP_NVDEC1 40
> > >
> > > I'm not sure this is right. The existing list is based on "Table 4:
> > > Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> > > none of these new swgroups seem to be present in that table.
> >
> > I went through all the MC_SMMU_XX_ASID_0 registers. All of
> > them have their own ASID registers that I added in PATCH-5.
>
> Thierry,
>
> Any follow ups on this topic? Does it require a fix or looks correct?
This does indeed look correct, based on what registers exist for these.
It'd be good to know how Nicolin expects these to be used, since these
are currently not listed in device tree. There's certainly some like
TSEC or NVDEC that we don't support (yet) upstream, but things like DC1
and HC1 already have equivalents that we use, so I'm not sure how we'll
integrate these new ones.
I suppose it doesn't really matter if any of these end up being unused,
so:
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 5/5] memory: tegra: Complete tegra210_swgroups
2020-10-08 0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
@ 2020-10-27 13:01 ` Thierry Reding
2020-10-27 23:37 ` Nicolin Chen
2020-11-20 16:27 ` Thierry Reding
2020-11-22 11:07 ` Krzysztof Kozlowski
2 siblings, 1 reply; 28+ messages in thread
From: Thierry Reding @ 2020-10-27 13:01 UTC (permalink / raw)
To: Nicolin Chen
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1547 bytes --]
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them to the list.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index b400802c9f14..b3bbc5a05ba1 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
> + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
Oddly enough I can see these in the TRM, but they are not in the
internal reference manuals that are supposed to be the canonical
reference for the TRM. Perhaps the TRM is out of date?
Thierry
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
2020-10-08 0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
2020-10-09 12:21 ` Thierry Reding
@ 2020-10-27 19:54 ` Krzysztof Kozlowski
1 sibling, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-27 19:54 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them in bindings.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
2020-10-27 12:55 ` Thierry Reding
@ 2020-10-27 23:31 ` Nicolin Chen
0 siblings, 0 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-27 23:31 UTC (permalink / raw)
To: Thierry Reding
Cc: Krzysztof Kozlowski, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Tue, Oct 27, 2020 at 01:55:06PM +0100, Thierry Reding wrote:
> This does indeed look correct, based on what registers exist for these.
> It'd be good to know how Nicolin expects these to be used, since these
> are currently not listed in device tree. There's certainly some like
Judging from our downstream code, I don't actually expect all of
them will be used, except some being used yet not got upstream.
> TSEC or NVDEC that we don't support (yet) upstream, but things like DC1
> and HC1 already have equivalents that we use, so I'm not sure how we'll
> integrate these new ones.
Downstream code groups those equivalents swgroups, so I think we
can do similarly using tegra_smmu_group_soc like the existing one
for display, if any of them gets upstream someday.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 5/5] memory: tegra: Complete tegra210_swgroups
2020-10-27 13:01 ` Thierry Reding
@ 2020-10-27 23:37 ` Nicolin Chen
0 siblings, 0 replies; 28+ messages in thread
From: Nicolin Chen @ 2020-10-27 23:37 UTC (permalink / raw)
To: Thierry Reding
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
On Tue, Oct 27, 2020 at 02:01:11PM +0100, Thierry Reding wrote:
> On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> > According to Tegra X1 TRM, there are missing swgroups in the
> > tegra210_swgroups list. So this patch adds them to the list.
> >
> > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > TEGRA_SWGROUP_GPU (in list) as it is.
> >
> > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > ---
> > drivers/memory/tegra/tegra210.c | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> > index b400802c9f14..b3bbc5a05ba1 100644
> > --- a/drivers/memory/tegra/tegra210.c
> > +++ b/drivers/memory/tegra/tegra210.c
> > @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> > { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> > { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> > + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
> > + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
>
> Oddly enough I can see these in the TRM, but they are not in the
> internal reference manuals that are supposed to be the canonical
> reference for the TRM. Perhaps the TRM is out of date?
Hmm..I actually have been using the TRM from official site all
the time. These two aren't being used downstream either; I put
them in the patch merely because they exist in the TRM. So we
may drop them if you feel that's better.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 5/5] memory: tegra: Complete tegra210_swgroups
2020-10-08 0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
2020-10-27 13:01 ` Thierry Reding
@ 2020-11-20 16:27 ` Thierry Reding
2020-11-22 11:07 ` Krzysztof Kozlowski
2 siblings, 0 replies; 28+ messages in thread
From: Thierry Reding @ 2020-11-20 16:27 UTC (permalink / raw)
To: Nicolin Chen
Cc: krzk, robh+dt, jonathanh, linux-tegra, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 696 bytes --]
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them to the list.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 5/5] memory: tegra: Complete tegra210_swgroups
2020-10-08 0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
2020-10-27 13:01 ` Thierry Reding
2020-11-20 16:27 ` Thierry Reding
@ 2020-11-22 11:07 ` Krzysztof Kozlowski
2 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2020-11-22 11:07 UTC (permalink / raw)
To: Nicolin Chen
Cc: thierry.reding, robh+dt, jonathanh, linux-tegra, devicetree,
linux-kernel
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them to the list.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> drivers/memory/tegra/tegra210.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2020-11-22 11:07 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-08 0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
2020-10-08 0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
2020-10-09 12:11 ` Thierry Reding
2020-10-26 20:14 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
2020-10-09 12:14 ` Thierry Reding
2020-10-26 20:15 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
2020-10-08 10:32 ` Krzysztof Kozlowski
2020-10-08 20:26 ` Nicolin Chen
2020-10-12 16:43 ` Krzysztof Kozlowski
2020-10-12 18:57 ` Nicolin Chen
2020-10-09 12:15 ` Thierry Reding
2020-10-26 20:17 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
2020-10-09 12:21 ` Thierry Reding
2020-10-09 15:52 ` Nicolin Chen
2020-10-26 20:17 ` Krzysztof Kozlowski
2020-10-27 12:55 ` Thierry Reding
2020-10-27 23:31 ` Nicolin Chen
2020-10-27 19:54 ` Krzysztof Kozlowski
2020-10-08 0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
2020-10-27 13:01 ` Thierry Reding
2020-10-27 23:37 ` Nicolin Chen
2020-11-20 16:27 ` Thierry Reding
2020-11-22 11:07 ` Krzysztof Kozlowski
2020-10-08 10:29 ` [PATCH 0/5] memory: tegra: Fix client list and add swgroups Krzysztof Kozlowski
2020-10-08 20:27 ` Nicolin Chen
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