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From: JC Kuo <jckuo@nvidia.com>
To: <gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>,
	<robh@kernel.org>, <jonathanh@nvidia.com>, <kishon@ti.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-usb@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<nkristam@nvidia.com>, JC Kuo <jckuo@nvidia.com>,
	Thierry Reding <treding@nvidia.com>
Subject: [PATCH v4 01/16] clk: tegra: Add PLLE HW power sequencer control
Date: Fri, 16 Oct 2020 21:07:11 +0800
Message-ID: <20201016130726.1378666-2-jckuo@nvidia.com> (raw)
In-Reply-To: <20201016130726.1378666-1-jckuo@nvidia.com>

PLLE has a hardware power sequencer logic which is a state machine
that can power on/off PLLE without any software intervention. The
sequencer has two inputs, one from XUSB UPHY PLL and the other from
SATA UPHY PLL. PLLE provides reference clock to XUSB and SATA UPHY
PLLs. When both of the downstream PLLs are powered-off, PLLE hardware
power sequencer will automatically power off PLLE for power saving.

XUSB and SATA UPHY PLLs also have their own hardware power sequencer
logic. XUSB UPHY PLL is shared between XUSB SuperSpeed ports and PCIE
controllers. The XUSB UPHY PLL hardware power sequencer has inputs
from XUSB and PCIE. When all of the XUSB SuperSpeed ports and PCIE
controllers are in low power state, XUSB UPHY PLL hardware power
sequencer automatically power off PLL and flags idle to PLLE hardware
power sequencer. Similar applies to SATA UPHY PLL.

PLLE hardware power sequencer has to be enabled after both downstream
sequencers are enabled.

This commit adds two helper functions:
1. tegra210_plle_hw_sequence_start() for XUSB PADCTL driver to enable
   PLLE hardware sequencer at proper time.

2. tegra210_plle_hw_sequence_is_enabled() for XUSB PADCTL driver to
   check whether PLLE hardware sequencer has been enabled or not.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
v4:
   update copyright strings
v3:
   rename 'val' with 'value

 drivers/clk/tegra/clk-tegra210.c | 53 +++++++++++++++++++++++++++++++-
 include/linux/clk/tegra.h        |  4 ++-
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 68cbb98af567..b9099012dc7b 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2020 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/io.h>
@@ -403,6 +403,14 @@ static unsigned long tegra210_input_freq[] = {
 #define PLLRE_BASE_DEFAULT_MASK		0x1c000000
 #define PLLRE_MISC0_WRITE_MASK		0x67ffffff
 
+/* PLLE */
+#define PLLE_MISC_IDDQ_SW_CTRL		(1 << 14)
+#define PLLE_AUX_USE_LOCKDET		(1 << 3)
+#define PLLE_AUX_SS_SEQ_INCLUDE		(1 << 31)
+#define PLLE_AUX_ENABLE_SWCTL		(1 << 4)
+#define PLLE_AUX_SS_SWCTL		(1 << 6)
+#define PLLE_AUX_SEQ_ENABLE		(1 << 24)
+
 /* PLLX */
 #define PLLX_USE_DYN_RAMP		1
 #define PLLX_BASE_LOCK			(1 << 27)
@@ -489,6 +497,49 @@ static unsigned long tegra210_input_freq[] = {
 #define PLLU_MISC0_WRITE_MASK		0xbfffffff
 #define PLLU_MISC1_WRITE_MASK		0x00000007
 
+bool tegra210_plle_hw_sequence_is_enabled(void)
+{
+	u32 value;
+
+	value = readl_relaxed(clk_base + PLLE_AUX);
+	if (value & PLLE_AUX_SEQ_ENABLE)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_is_enabled);
+
+int tegra210_plle_hw_sequence_start(void)
+{
+	u32 value;
+
+	if (tegra210_plle_hw_sequence_is_enabled())
+		return 0;
+
+	/* skip if PLLE is not enabled yet */
+	value = readl_relaxed(clk_base + PLLE_MISC0);
+	if (!(value & PLLE_MISC_LOCK))
+		return -EIO;
+
+	value &= ~PLLE_MISC_IDDQ_SW_CTRL;
+	writel_relaxed(value, clk_base + PLLE_MISC0);
+
+	value = readl_relaxed(clk_base + PLLE_AUX);
+	value |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
+	value &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
+	writel_relaxed(value, clk_base + PLLE_AUX);
+
+	fence_udelay(1, clk_base);
+
+	value |= PLLE_AUX_SEQ_ENABLE;
+	writel_relaxed(value, clk_base + PLLE_AUX);
+
+	fence_udelay(1, clk_base);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_start);
+
 void tegra210_xusb_pll_hw_control_enable(void)
 {
 	u32 val;
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3f01d43f0598..7be477377ad3 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2020, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #ifndef __LINUX_CLK_TEGRA_H_
@@ -123,6 +123,8 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
+extern int tegra210_plle_hw_sequence_start(void);
+extern bool tegra210_plle_hw_sequence_is_enabled(void);
 extern void tegra210_xusb_pll_hw_control_enable(void);
 extern void tegra210_xusb_pll_hw_sequence_start(void);
 extern void tegra210_sata_pll_hw_control_enable(void);
-- 
2.25.1


  reply index

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-16 13:07 [PATCH v4 00/16] Tegra XHCI controller ELPG support JC Kuo
2020-10-16 13:07 ` JC Kuo [this message]
2020-10-16 13:07 ` [PATCH v4 02/16] clk: tegra: Don't enable PLLE HW sequencer at init JC Kuo
2020-10-16 13:07 ` [PATCH v4 03/16] phy: tegra: xusb: Move usb3 port init for Tegra210 JC Kuo
2020-10-16 13:07 ` [PATCH v4 04/16] phy: tegra: xusb: tegra210: Do not reset UPHY PLL JC Kuo
2020-10-16 13:07 ` [PATCH v4 05/16] phy: tegra: xusb: Rearrange UPHY init on Tegra210 JC Kuo
2020-10-16 13:07 ` [PATCH v4 06/16] phy: tegra: xusb: Add Tegra210 lane_iddq operation JC Kuo
2020-10-16 13:07 ` [PATCH v4 07/16] phy: tegra: xusb: Add sleepwalk and suspend/resume JC Kuo
2020-10-16 13:07 ` [PATCH v4 08/16] soc/tegra: pmc: Provide USB sleepwalk register map JC Kuo
2020-10-16 13:07 ` [PATCH v4 09/16] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
2020-10-16 13:07 ` [PATCH v4 10/16] dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop JC Kuo
2020-10-19 21:40   ` Rob Herring
2020-10-28  9:18     ` JC Kuo
2020-11-13 16:20     ` Thierry Reding
2020-11-19  5:28       ` JC Kuo
2020-10-16 13:07 ` [PATCH v4 11/16] phy: tegra: xusb: Add wake/sleepwalk for Tegra210 JC Kuo
2020-10-16 13:07 ` [PATCH v4 12/16] phy: tegra: xusb: Tegra210 host mode VBUS control JC Kuo
2020-10-16 13:07 ` [PATCH v4 13/16] phy: tegra: xusb: Add wake/sleepwalk for Tegra186 JC Kuo
2020-10-16 13:07 ` [PATCH v4 14/16] arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq JC Kuo
2020-10-16 13:07 ` [PATCH v4 15/16] usb: host: xhci-tegra: Unlink power domain devices JC Kuo
2020-10-16 13:07 ` [PATCH v4 16/16] xhci: tegra: Enable ELPG for runtime/system PM JC Kuo
2020-10-27  6:10   ` kernel test robot
2020-11-13 16:44 ` [PATCH v4 00/16] Tegra XHCI controller ELPG support Thierry Reding
2020-11-17  6:14   ` JC Kuo

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