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Fri, 13 Nov 2020 08:35:53 -0800 (PST) Date: Fri, 13 Nov 2020 17:35:52 +0100 From: Thierry Reding To: Dmitry Osipenko Cc: Ulf Hansson , Viresh Kumar , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet , linux-samsung-soc , driverdevel , Linux USB List , linux-pwm@vger.kernel.org, "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List , DTML , dri-devel , Linux Media Mailing List , linux-tegra Subject: Re: [PATCH v1 00/30] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs Message-ID: <20201113163552.GE1408970@ulmo> References: <20201104234427.26477-1-digetx@gmail.com> <2716c195-083a-112f-f1e5-2f6b7152a4b5@gmail.com> <1f7e90c4-6134-2e2b-4869-5afbda18ead3@gmail.com> <20201112204358.GA1027187@ulmo> <25942da9-b527-c0aa-5403-53c9cc34ad93@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="KuLpqunXa7jZSBt+" Content-Disposition: inline In-Reply-To: <25942da9-b527-c0aa-5403-53c9cc34ad93@gmail.com> User-Agent: Mutt/1.14.7 (2020-08-29) Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org --KuLpqunXa7jZSBt+ Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Nov 13, 2020 at 01:14:45AM +0300, Dmitry Osipenko wrote: > 12.11.2020 23:43, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > >> The difference in comparison to using voltage regulator directly is > >> minimal, basically the core-supply phandle is replaced is replaced with > >> a power-domain phandle in a device tree. > > These new power-domain handles would have to be added to devices that > > potentially already have a power-domain handle, right? Isn't that going > > to cause issues? I vaguely recall that we already have multiple power > > domains for the XUSB controller and we have to jump through extra hoops > > to make that work. >=20 > I modeled the core PD as a parent of the PMC sub-domains, which > presumably is a correct way to represent the domains topology. >=20 > https://gist.github.com/digetx/dfd92c7f7e0aa6cef20403c4298088d7 >=20 > >> The only thing which makes me feel a bit uncomfortable is that there is > >> no real hardware node for the power domain node in a device-tree. > > Could we anchor the new power domain at the PMC for example? That would > > allow us to avoid the "virtual" node. >=20 > I had a thought about using PMC for the core domain, but not sure > whether it will be an entirely correct hardware description. Although, > it will be nice to have it this way. >=20 > This is what Tegra TRM says about PMC: >=20 > "The Power Management Controller (PMC) block interacts with an external > or Power Manager Unit (PMU). The PMC mostly controls the entry and exit > of the system from different sleep modes. It provides power-gating > controllers for SOC and CPU power-islands and also provides scratch > storage to save some of the context during sleep modes (when CPU and/or > SOC power rails are off). Additionally, PMC interacts with the external > Power Manager Unit (PMU)." >=20 > The core voltage regulator is a part of the PMU. >=20 > Not all core SoC devices are behind PMC, IIUC. There are usually some SoC devices that are always-on. Things like the RTC for example, can never be power-gated, as far as I recall. On newer chips there are usually many more blocks that can't be powergated at all. > > On the other hand, if we were to > > use a regulator, we'd be adding a node for that, right? So isn't this > > effectively going to be the same node if we use a power domain? Both > > software constructs are using the same voltage regulator, so they should > > be able to be described by the same device tree node, shouldn't they? >=20 > I'm not exactly sure what you're meaning by "use a regulator" and "we'd > be adding a node for that", could you please clarify? This v1 approach > uses a core-supply phandle (i.e. regulator is used), it doesn't require > extra nodes. What I meant to say was that the actual supply voltage is generated by some device (typically one of the SD outputs of the PMIC). Whether we model this as a power domain or a regulator doesn't really matter, right? So I'm wondering if the device that generates the voltage should be the power domain provider, just like it is the provider of the regulator if this was modelled as a regulator. Thierry --KuLpqunXa7jZSBt+ Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl+uteUACgkQ3SOs138+ s6HFrg//XUCBi+MoTYKA9Q0nyyDEbz8pB7xsPWf9AWJHRToygKc0DTU1ZaPQLNp+ zx+Yg2HSEBBzzv1c5cABiz0dUaE+gkzTfY74+wByGBumAiPaFCOmamm3fwgTlzsM ZzTrLxJShO6bIo12gq98qI68RxlwptdQcGagjc4QLcaL1xxhdyYiEFtQj8X3rwfp r2ELceMzT3klMTV34ghkgQKBRkgxm3thCmk+O/+scUwM9ju23OeClHBPsq+YwWz/ ItCwLTUXyfPTSzIqXbjPEGXPbNGS2aUdYo0YsY42Q5XswBGPGXV+VgCPd153Vyek x+tAG0YSkV3NWFIQKBR5iwvguqZbVYgBR8tonT+LH9qyx6wADX2bp1VtEssD3Dsq qWc7y+PnmrUkx895JcxYLzhGoN5Hr3xwKeTLSRxGCQQvh1fqJJO4Ja4QnBdxK1lm FLLCPrq0/yK+o6DKJnAWjBcVyWfY4z2MPej6lao9ZlR4nC0qaY9URhD//kujuB7R dsRKyAwamYzw0b1doZWjffloEhog7WbjMw8UsbF+E8K7kSNePUqgaWWMsZDwh6yI VrszC62dJzCUMweS9s2mSjQ08xGrcITA8i2qxMKpRQA6VoZzMAdP6WjxseQoDa4g 6Rsyr9Mt8Ed+Gs4vssp8C6jeFDQEGXM+37kYIC8LrNM21HZoq74= =p82m -----END PGP SIGNATURE----- --KuLpqunXa7jZSBt+--