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Mon, 29 May 2023 06:58:16 -0700 From: Peter De Schrijver To: Peter De Schrijver , , , CC: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joe Perches , , , , Conor Dooley Subject: [PATCH v5 4/5] dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCs Date: Mon, 29 May 2023 16:50:49 +0300 Message-ID: <20230529135044.2746339-5-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529135044.2746339-1-pdeschrijver@nvidia.com> References: <20230529135044.2746339-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT096:EE_|PH0PR12MB8176:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d95b816-2c2a-4649-52d8-08db604cc648 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SNABfjEdBjWEAYNA13OOULzqDvpbM2wEUOQxJIG6C9b2CiTFt0GA4rkG67wVVnTDaNAU3oIr1R/XAwQpp2iKKgcIIFWG+BMo7k9Wam/SPdji4xy1TMXZZ4bh3JuvS1x3AZ9NmPHNzDo4ES/i04kj+0g6oD4uEVeoYYWg0mSNGy/SsltJ2YaeQyzjIZaklL11iR8TmNVfJ1P8862t5j8pudIE8tTB8EwwS4xXkDR3NE42PwYHl2Xnc3S3mQOrH1wLEvd7NdQFGx+gtmTUoTufkGEc57QvylF66sAPjx5LkUM9DBLUBczILcF2DQVaIMcndn8snxz3sq5us0XdsuLA8C2B9n4F8pDahso/ZElz/bIXpPQgUe0Qp53sxFTtqxH2d2PfEw5NSt17nylQ7aQDfUDi25VMrPHy5JsqzWX9HwRcB2pZ7q7clr0q14FvmJBZBpnKr/kiUg4Clu9Wsp6bH65gTue18NSV1XLSXOC/0DgADT341GumfnxdBhxuK3HT/9XpdvD73uqe+ZoGQu4Z4lAeK4JyFtdfH5PhdEvS9I3b1Mfk8v+JRCZb2O/A0QwEpxVlB11Ck7xv0nZlQX0WVUR/0eTxr6ILXdnnMgtisI0waowTzukq7Ik0ZPzhYa6qqXI7aroR1VIT1JFZuiw66Qnf/tcBSoj/fLo8wDGtKSD63OBzIb15mpWc3JLJcslbK+1gk4Ck7yykf4xvYvbQeSa0ZSsBiyX8V1QRrxLvBgZv99//yuKtZ7GR4/eaAtcN X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(346002)(376002)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(54906003)(478600001)(110136005)(40460700003)(8676002)(8936002)(5660300002)(7416002)(2906002)(86362001)(36756003)(82310400005)(70206006)(70586007)(4326008)(6636002)(82740400003)(356005)(316002)(7636003)(40480700001)(41300700001)(186003)(36860700001)(1076003)(26005)(47076005)(7696005)(426003)(6666004)(336012)(83380400001)(2616005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2023 13:58:26.2529 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d95b816-2c2a-4649-52d8-08db604cc648 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8176 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver Reviewed-by: Conor Dooley --- .../firmware/nvidia,tegra186-bpmp.yaml | 39 ++++++++++++++++--- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml index 833c07f1685c..c43d17f6e96b 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -57,8 +57,11 @@ description: | "#address-cells" or "#size-cells" property. The shared memory area for the IPC TX and RX between CPU and BPMP are - predefined and work on top of sysram, which is an SRAM inside the - chip. See ".../sram/sram.yaml" for the bindings. + predefined and work on top of either sysram, which is an SRAM inside the + chip, or in normal SDRAM. + See ".../sram/sram.yaml" for the bindings for the SRAM case. + See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for + the SDRAM case. properties: compatible: @@ -81,6 +84,11 @@ properties: minItems: 2 maxItems: 2 + memory-region: + description: phandle to reserved memory region used for IPC between + CPU-NS and BPMP. + maxItems: 1 + "#clock-cells": const: 1 @@ -115,10 +123,15 @@ properties: additionalProperties: false +oneOf: + - required: + - memory-region + - required: + - shmem + required: - compatible - mboxes - - shmem - "#clock-cells" - "#power-domain-cells" - "#reset-cells" @@ -165,8 +178,7 @@ examples: <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names = "read", "write", "dma-mem", "dma-write"; iommus = <&smmu TEGRA186_SID_BPMP>; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #power-domain-cells = <1>; @@ -184,3 +196,20 @@ examples: #thermal-sensor-cells = <1>; }; }; + + - | + #include + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; + memory-region = <&dram_cpu_bpmp_mail>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; -- 2.34.1