From: Sumit Gupta <sumitg@nvidia.com>
To: <krzysztof.kozlowski@linaro.org>, <treding@nvidia.com>,
<jonathanh@nvidia.com>, <linux-kernel@vger.kernel.org>,
<linux-tegra@vger.kernel.org>
Cc: <bbasu@nvidia.com>, <talho@nvidia.com>, <sumitg@nvidia.com>
Subject: [Patch 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets
Date: Wed, 21 Jun 2023 19:05:24 +0530 [thread overview]
Message-ID: <20230621133526.22492-2-sumitg@nvidia.com> (raw)
In-Reply-To: <20230621133526.22492-1-sumitg@nvidia.com>
Sort the MC client entries in "tegra234_mc_clients" table as per the
override and security register offsets. This will help to avoid
creating duplicate entries.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/memory/tegra/tegra234.c | 514 ++++++++++++++++----------------
1 file changed, 259 insertions(+), 255 deletions(-)
diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index 8e873a7bc34f..3e44efe4541e 100644
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -12,6 +12,10 @@
#include <soc/tegra/bpmp.h>
#include "mc.h"
+/*
+ * MC Client entries are sorted in the increasing order of the
+ * override and security register offsets.
+ */
static const struct tegra_mc_client tegra234_mc_clients[] = {
{
.id = TEGRA234_MEMORY_CLIENT_HDAR,
@@ -25,6 +29,106 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0xac,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
+ .name = "pcie6ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x140,
+ .security = 0x144,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
+ .name = "pcie6aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x148,
+ .security = 0x14c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
+ .name = "pcie7ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x150,
+ .security = 0x154,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
+ .name = "dla0rdb",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x160,
+ .security = 0x164,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
+ .name = "dla0rdb1",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x168,
+ .security = 0x16c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
+ .name = "dla0wrb",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x170,
+ .security = 0x174,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
+ .name = "dla0rdb",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x178,
+ .security = 0x17c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
+ .name = "pcie7aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x180,
+ .security = 0x184,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
+ .name = "pcie8ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE8,
+ .regs = {
+ .sid = {
+ .override = 0x190,
+ .security = 0x194,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_HDAW,
.name = "hdaw",
@@ -37,6 +141,102 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x1ac,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
+ .name = "pcie8aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE8,
+ .regs = {
+ .sid = {
+ .override = 0x1d8,
+ .security = 0x1dc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
+ .name = "pcie9ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE9,
+ .regs = {
+ .sid = {
+ .override = 0x1e0,
+ .security = 0x1e4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
+ .name = "pcie6ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x1e8,
+ .security = 0x1ec,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
+ .name = "pcie9aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE9,
+ .regs = {
+ .sid = {
+ .override = 0x1f0,
+ .security = 0x1f4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
+ .name = "pcie10ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x1f8,
+ .security = 0x1fc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
+ .name = "pcie10aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x200,
+ .security = 0x204,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
+ .name = "pcie10ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x240,
+ .security = 0x244,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
+ .name = "pcie7ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x248,
+ .security = 0x24c,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
.name = "mgbeard",
@@ -157,6 +357,26 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x33c,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
+ .name = "dla0rdb1",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x370,
+ .security = 0x374,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
+ .name = "dla0wrb",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x378,
+ .security = 0x37c,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_VI2W,
.name = "vi2w",
@@ -181,18 +401,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x38c,
},
},
- }, {
- .id = TEGRA234_MEMORY_CLIENT_VI2FALW,
- .name = "vi2falw",
- .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
- .type = TEGRA_ICC_ISO_VIFAL,
- .sid = TEGRA234_SID_ISO_VI2FALC,
- .regs = {
- .sid = {
- .override = 0x3e0,
- .security = 0x3e4,
- },
- },
}, {
.id = TEGRA234_MEMORY_CLIENT_APER,
.name = "aper",
@@ -218,27 +426,27 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
- .name = "nvdisplayr",
- .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
- .type = TEGRA_ICC_ISO_DISPLAY,
- .sid = TEGRA234_SID_ISO_NVDISPLAY,
+ .id = TEGRA234_MEMORY_CLIENT_VI2FALW,
+ .name = "vi2falw",
+ .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
+ .type = TEGRA_ICC_ISO_VIFAL,
+ .sid = TEGRA234_SID_ISO_VI2FALC,
.regs = {
.sid = {
- .override = 0x490,
- .security = 0x494,
+ .override = 0x3e0,
+ .security = 0x3e4,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
- .name = "nvdisplayr1",
+ .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
+ .name = "nvdisplayr",
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
.type = TEGRA_ICC_ISO_DISPLAY,
.sid = TEGRA234_SID_ISO_NVDISPLAY,
.regs = {
.sid = {
- .override = 0x508,
- .security = 0x50c,
+ .override = 0x490,
+ .security = 0x494,
},
},
}, {
@@ -305,6 +513,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x504,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
+ .name = "nvdisplayr1",
+ .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
+ .type = TEGRA_ICC_ISO_DISPLAY,
+ .sid = TEGRA234_SID_ISO_NVDISPLAY,
+ .regs = {
+ .sid = {
+ .override = 0x508,
+ .security = 0x50c,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
@@ -335,26 +555,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x604,
},
},
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
- .name = "dla0rdb",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x160,
- .security = 0x164,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
- .name = "dla0rda1",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x748,
- .security = 0x74c,
- },
- },
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
@@ -365,26 +565,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x60c,
},
},
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
- .name = "dla0rdb1",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x168,
- .security = 0x16c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
- .name = "dla0wrb",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x170,
- .security = 0x174,
- },
- },
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
.name = "dla0rda",
@@ -415,26 +595,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x624,
},
},
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
- .name = "dla0rdb",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x178,
- .security = 0x17c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
- .name = "dla0rda1",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x750,
- .security = 0x754,
- },
- },
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla0falwrb",
@@ -445,26 +605,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x62c,
},
},
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
- .name = "dla0rdb1",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x370,
- .security = 0x374,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
- .name = "dla0wrb",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x378,
- .security = 0x37c,
- },
- },
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
.name = "pcie0r",
@@ -610,171 +750,35 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
- .name = "pcie5r1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE5,
- .regs = {
- .sid = {
- .override = 0x778,
- .security = 0x77c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
- .name = "pcie6ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x140,
- .security = 0x144,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
- .name = "pcie6aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x148,
- .security = 0x14c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
- .name = "pcie6ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x1e8,
- .security = 0x1ec,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
- .name = "pcie7ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x150,
- .security = 0x154,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
- .name = "pcie7aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x180,
- .security = 0x184,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
- .name = "pcie7ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x248,
- .security = 0x24c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
- .name = "pcie8ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE8,
- .regs = {
- .sid = {
- .override = 0x190,
- .security = 0x194,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
- .name = "pcie8aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE8,
- .regs = {
- .sid = {
- .override = 0x1d8,
- .security = 0x1dc,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
- .name = "pcie9ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE9,
- .regs = {
- .sid = {
- .override = 0x1e0,
- .security = 0x1e4,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
- .name = "pcie9aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE9,
- .regs = {
- .sid = {
- .override = 0x1f0,
- .security = 0x1f4,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
- .name = "pcie10ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
+ .name = "dla0rda1",
+ .sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
- .override = 0x1f8,
- .security = 0x1fc,
+ .override = 0x748,
+ .security = 0x74c,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
- .name = "pcie10aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
+ .name = "dla0rda1",
+ .sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
- .override = 0x200,
- .security = 0x204,
+ .override = 0x750,
+ .security = 0x754,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
- .name = "pcie10ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
+ .name = "pcie5r1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
.type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .sid = TEGRA234_SID_PCIE5,
.regs = {
.sid = {
- .override = 0x240,
- .security = 0x244,
+ .override = 0x778,
+ .security = 0x77c,
},
},
}, {
--
2.17.1
next prev parent reply other threads:[~2023-06-21 13:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 13:35 [Patch 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta
2023-06-21 13:35 ` Sumit Gupta [this message]
2023-06-21 13:35 ` [Patch 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Sumit Gupta
2023-06-21 13:35 ` [Patch 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported Sumit Gupta
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