Re: [PATCH v5 0/6] Add Tegra241 (Grace) CMDQV Support (part 1/2)

From: Jason Gunthorpe <jgg@nvidia.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
	thierry.reding@gmail.com, vdumpa@nvidia.com,
	jonathanh@nvidia.com, linux-kernel@vger.kernel.org,
	iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	Jerry Snitselaar <jsnitsel@redhat.com>
Subject: Re: [PATCH v5 0/6] Add Tegra241 (Grace) CMDQV Support (part 1/2)
Date: Mon, 15 Apr 2024 14:14:26 -0300	[thread overview]
Message-ID: <20240415171426.GF3637727@nvidia.com> (raw)
In-Reply-To: <cover.1712977210.git.nicolinc@nvidia.com>

On Fri, Apr 12, 2024 at 08:43:48PM -0700, Nicolin Chen wrote:

> The user-space support is to provide uAPIs (via IOMMUFD) for hypervisors
> in user space to passthrough VCMDQs to VMs, allowing these VMs to access
> the VCMDQs directly without trappings, i.e. no VM Exits. This gives huge
> performance improvements: 70% to 90% reductions of TLB invalidation time
> were measured by various DMA unmap tests running in a guest OS, compared
> to a nested SMMU CMDQ (with trappings).

So everyone is on the same page, this is the primary point of this
series. The huge speed up of in-VM performance is necessary for the
workloads this chip is expected to be running. This series is unique
from all the rest because it runs inside a VM, often in the from of a
distro release.

It doesn't need the other series or it's own part 2 as it entirely
stands alone on bare metal hardware or on top of commercial VM cloud
instances runing who-knows-what in their hypervisors.

The other parts are substantially about enabling qemu and the open
ecosystem to have fully functional vSMMU3 virtualization.

Jason