From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B727C433E3 for ; Thu, 6 Aug 2020 18:52:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FAB720716 for ; Thu, 6 Aug 2020 18:52:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="TVW6GZDZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725927AbgHFSv6 (ORCPT ); Thu, 6 Aug 2020 14:51:58 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:6689 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728341AbgHFSv6 (ORCPT ); Thu, 6 Aug 2020 14:51:58 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 06 Aug 2020 11:50:17 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 06 Aug 2020 11:51:58 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 06 Aug 2020 11:51:58 -0700 Received: from [10.2.172.190] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 6 Aug 2020 18:51:56 +0000 Subject: Re: [PATCH v8 08/10] gpu: host1x: mipi: Keep MIPI clock enabled till calibration is done From: Sowjanya Komatineni To: Dmitry Osipenko , Thierry Reding CC: , , , , , , , , , , References: <1596469346-937-1-git-send-email-skomatineni@nvidia.com> <9ef0b875-e826-43e2-207e-168d2081ff6a@nvidia.com> <4689cfe9-e7c4-48bf-217f-3a31b59b8bda@nvidia.com> <0e78c5ca-c529-1e98-891d-30351c9aae81@gmail.com> <309e3b66-9288-91ef-71b4-be73eacbbd62@nvidia.com> <4025a458-fa78-924d-c84f-166f82df0f8e@gmail.com> <4f15d655-3d62-cf9f-82da-eae379d60fa6@nvidia.com> <412f8c53-1aca-db31-99a1-a0ecb2081ca5@nvidia.com> <61275bd6-58e7-887f-aa7d-8e60895e7b2b@nvidia.com> <6ff57c38-9847-42b0-643b-0d167c13779f@gmail.com> <26ed2841-db5d-aeb0-11c7-cbe2ddd1d76b@gmail.com> <50aa439e-a572-ce77-9d06-e060304b9bd4@nvidia.com> Message-ID: <3a4be8e9-32a5-e7d8-8727-8d860368bc8e@nvidia.com> Date: Thu, 6 Aug 2020 11:51:59 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <50aa439e-a572-ce77-9d06-e060304b9bd4@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596739817; bh=sNS7CrF9bquAWxzjW1qwHZX1tFt2IjxwG+MjH4EMj3w=; h=X-PGP-Universal:Subject:From:To:CC:References:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=TVW6GZDZ9RUuNdZotheXeFv4tesHNIADrW44ms1F9qHg85GLLMeuZF0CAENhanDlF /6VT6uqzGVHcnjTPky4S1fUCVnT2GIACPHnH4PSeT7pAPmhygxlYY5rPFW0j24bvSi zx3s/iIohm7PW9TbHJ0bQF0CeH+J9Se9Um3bni8zBlQDXa6VQ2O3FDpo5wgqck1K5l 4G2bRhYE8UXakyQ8vTYiLKfzUtN8t47JOBptjUGMXrYWsHdTxg8Kpc8J7g82FWu/3h DBdbMZ1bHyMl3vYM4xUnCoNsNgNQOVj7uuc6Em7jjo9O2htyibMfCd8tIPkyEI6P3r 2S8r+0/rFtlYA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On 8/6/20 11:44 AM, Sowjanya Komatineni wrote: > > On 8/6/20 11:18 AM, Dmitry Osipenko wrote: >> 06.08.2020 21:07, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>> On 8/6/20 11:01 AM, Dmitry Osipenko wrote: >>>> 06.08.2020 20:52, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> ... >>>>> Right mutex_unlock should happen at end of finish_calibration. >>>>> >>>>> With keeping mutex locked in start, we dont have to check for=20 >>>>> active to >>>>> be 0 to issue start as mutex will keep it locked and other pads >>>>> calibration can only go thru when current one is done. >>>>> >>>>> So instead of below sequence, its simpler to do this way? >>>>> >>>>> start_calibration() >>>>> >>>>> - mutex_lock >>>>> >>>>> - wait for 72uS after start >>>>> >>>>> finish_calibration() >>>>> >>>>> - keep check for ACTIVE =3D 0 and DONE =3D 1 >>>> I think only the DONE bits which correspond to the mipi_device->pads >>>> bitmask should be awaited. >>> As next START can't be triggered when auto cal is ACTIVE, we should=20 >>> keep >>> this in finish. >>> >>> As we do mutex_unlock only at end of finish, other pads calibrations >>> dont go thru till the one in process is finished. >>> >>> So in this case ACTIVE applies to current selected pads that are under >>> calibration. >> Should be better to check only the relevant bits in order to catch bugs, >> otherwise you may get a DONE status from the irrelevant pads. > tegra_mipi_device is separate for DSI and CSI channels. mutex lock=20 > used during calibrate is device specific lock. > So, it will not prevent other devices to hold till on going=20 > calibration is done unless we add wait for active bit before=20 > triggering start. > > Currently we wait for active bit at end during calibration done check=20 > after start trigger. But when other devices go thru calibration in=20 > parallel as lock is device specific and not common lock for all=20 > devices it will trigger start but MIPI calibration logic ignore if=20 > previous calibration is still in progress. > > Need to serialize calibration start requests from different devices=20 > based on ACTIVE bit. Sorry confused. MIPI driver is using common lock from tegra_mipi for all=20 tegra_mipi_device So should be ok as only one device start_calibration can happen at a time. But its still good to check ACTIVE is cleared and to report as error if=20 not as ACTIVE will be cleared once set of pads enabled for this calibration= . Eg: CSI port can be 4 lane and all 4 pads gets enabled at same time and=20 with this ACTIVE should still be verified to be 0 to make sure all pads=20 calibration is done > >>>> Perhaps the start_calibration() also needs to be changed to not touch >>>> the MIPI_CAL_CONFIG bits of the unrelated pads? >>> Driver already takes care of programming corresponding pads config=20 >>> only. >> It writes 0 to the config of the unrelated pads, which probably isn't >> nice if some pads use periodic auto-calibration. >> >> https://elixir.bootlin.com/linux/v5.8/source/drivers/gpu/host1x/mipi.c#L= 350=20 >> >> >> Although looks like auto-calibration isn't supported by the current=20 >> driver. > > Yes we don't use auto-calibration. > > Only common bit here is MIPI_CAL_CTRL start. All others are pad=20 > specific currently. >