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* [PATCH] arm64: tegra: Properly size register regions for GPU on Tegra194
@ 2020-07-21 15:10 Thierry Reding
  2020-07-24 23:29 ` Terje Bergstrom
  0 siblings, 1 reply; 2+ messages in thread
From: Thierry Reding @ 2020-07-21 15:10 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Jon Hunter, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Terje Bergström

From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather
than 256 MiB.

Reported-by: Terje Bergström <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 48160f48003a..fc36d683049b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1398,8 +1398,8 @@ sor3: sor@15bc0000 {
 
 		gpu@17000000 {
 			compatible = "nvidia,gv11b";
-			reg = <0x17000000 0x10000000>,
-			      <0x18000000 0x10000000>;
+			reg = <0x17000000 0x1000000>,
+			      <0x18000000 0x1000000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "stall", "nonstall";
-- 
2.27.0

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] arm64: tegra: Properly size register regions for GPU on Tegra194
  2020-07-21 15:10 [PATCH] arm64: tegra: Properly size register regions for GPU on Tegra194 Thierry Reding
@ 2020-07-24 23:29 ` Terje Bergstrom
  0 siblings, 0 replies; 2+ messages in thread
From: Terje Bergstrom @ 2020-07-24 23:29 UTC (permalink / raw)
  To: Thierry Reding; +Cc: Jon Hunter, linux-tegra

On 7/21/2020 8:10 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather
> than 256 MiB.
>
> Reported-by: Terje Bergström <tbergstrom@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 48160f48003a..fc36d683049b 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1398,8 +1398,8 @@ sor3: sor@15bc0000 {
>   
>   		gpu@17000000 {
>   			compatible = "nvidia,gv11b";
> -			reg = <0x17000000 0x10000000>,
> -			      <0x18000000 0x10000000>;
> +			reg = <0x17000000 0x1000000>,
> +			      <0x18000000 0x1000000>;
>   			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>   			interrupt-names = "stall", "nonstall";

Looks good to me.

Reviewed-By: Terje Bergström <tbergstrom@nvidia.com>

Terje


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2020-07-21 15:10 [PATCH] arm64: tegra: Properly size register regions for GPU on Tegra194 Thierry Reding
2020-07-24 23:29 ` Terje Bergstrom

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