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Thu, 23 Sep 2021 13:20:35 +0000 Received: from [10.26.49.14] (172.20.187.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 23 Sep 2021 13:20:32 +0000 Subject: Re: [PATCH v6 2/4] dmaengine: tegra: Add tegra gpcdma driver To: Akhil R CC: "dan.j.williams@intel.com" , "dmaengine@vger.kernel.org" , Krishna Yarlagadda , Laxman Dewangan , "linux-kernel@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "p.zabel@pengutronix.de" , Rajesh Gumasta , "thierry.reding@gmail.com" , "vkoul@kernel.org" , Pavan Kunapuli References: <1631887887-18967-1-git-send-email-akhilrajeev@nvidia.com> <1631887887-18967-3-git-send-email-akhilrajeev@nvidia.com> <5a3de015-a0d1-4440-12d0-06297ac7f9d0@nvidia.com> From: Jon Hunter Message-ID: Date: Thu, 23 Sep 2021 14:20:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 24f3d5cd-2e60-44c8-c3b0-08d97e94edbf X-MS-TrafficTypeDiagnostic: DM6PR12MB4185: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2021 13:20:35.7613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24f3d5cd-2e60-44c8-c3b0-08d97e94edbf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4185 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On 23/09/2021 13:51, Akhil R wrote: >> On 22/09/2021 15:46, Akhil R wrote: >>> >>>> On 17/09/2021 15:11, Akhil R wrote: >>>>> +static int tegra_dma_slave_config(struct dma_chan *dc, >>>>> + struct dma_slave_config *sconfig) { >>>>> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); >>>>> + >>>>> + if (tdc->dma_desc) { >>>>> + dev_err(tdc2dev(tdc), "Configuration not allowed\n"); >>>>> + return -EBUSY; >>>>> + } >>>>> + >>>>> + memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); >>>>> + if (tdc->slave_id == -1) >>>>> + tdc->slave_id = sconfig->slave_id; >>>>> + >>>>> + tdc->config_init = true; >>>>> + return 0; >>>>> +} >>>> >>>> So you have a function to reserve a slave ID, but you don't check >>>> here if it is already reserved. >>> slave-id is reserved considering the direction as well. >>> 'direction' is available only during prep_slave_sg function, I guess. >> >> Sorry I don't understand what you mean by that. > I mean, it would not be possible to check if the sid is in use without knowing > if the direction is MEM_TO_DEV or DEV_TO_MEM. The bitmask to check the > sid reservation is separate for MEM_TO_DEV and DEV_TO_MEM. > To get the direction parameter, we would need to wait till dma_prep_slave_sg > is called, I guess. I saw in the documentation that the 'direction' element in > dma_slave_config struct is deprecated and should use the value passed to > dma_prep_slave_sg(). Do we even need to worry about slave_id here? Typically the slave_id is coming from device-tree and so is handled by tegra_dma_of_xlate(). I would drop this unless there is an actual use-case we need to support that uses this. Jon -- nvpublic