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Tue, 29 Sep 2020 18:25:37 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 29 Sep 2020 18:25:37 +0100 From: Marc Zyngier To: Jon Hunter Cc: Jisheng Zhang , Kunihiko Hayashi , Neil Armstrong , linux-pci@vger.kernel.org, Binghui Wang , Bjorn Andersson , Masahiro Yamada , Thierry Reding , linux-arm-kernel@axis.com, Vidya Sagar , Fabio Estevam , Jerome Brunet , Rob Herring , Jesper Nilsson , Lorenzo Pieralisi , Kevin Hilman , Pratyush Anand , linux-tegra@vger.kernel.org, Krzysztof Kozlowski , Kishon Vijay Abraham I , Kukjin Kim , NXP Linux Team , Xiaowei Song , Richard Zhu , Martin Blumenstingl , linux-arm-msm@vger.kernel.org, Sascha Hauer , Yue Wang , linux-samsung-soc@vger.kernel.org, Bjorn Helgaas , linux-amlogic@lists.infradead.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jingoo Han , Andy Gross , linux-kernel@vger.kernel.org, Stanimir Varbanov , Pengutronix Kernel Team , Gustavo Pimentel , Shawn Guo , Lucas Stach Subject: Re: [PATCH v2 0/5] PCI: dwc: improve msi handling In-Reply-To: <8e06a370-a37a-5f33-b43b-2830adb31b3e@nvidia.com> References: <20200924190421.549cb8fc@xhacker.debian> <20200929184851.22682ff1@xhacker.debian> <8e06a370-a37a-5f33-b43b-2830adb31b3e@nvidia.com> User-Agent: Roundcube Webmail/1.4.8 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: jonathanh@nvidia.com, Jisheng.Zhang@synaptics.com, hayashi.kunihiko@socionext.com, narmstrong@baylibre.com, linux-pci@vger.kernel.org, wangbinghui@hisilicon.com, bjorn.andersson@linaro.org, yamada.masahiro@socionext.com, thierry.reding@gmail.com, linux-arm-kernel@axis.com, vidyas@nvidia.com, festevam@gmail.com, jbrunet@baylibre.com, robh@kernel.org, jesper.nilsson@axis.com, lorenzo.pieralisi@arm.com, khilman@baylibre.com, pratyush.anand@gmail.com, linux-tegra@vger.kernel.org, krzk@kernel.org, kishon@ti.com, kgene@kernel.org, linux-imx@nxp.com, songxiaowei@hisilicon.com, hongxing.zhu@nxp.com, martin.blumenstingl@googlemail.com, linux-arm-msm@vger.kernel.org, s.hauer@pengutronix.de, yue.wang@amlogic.com, linux-samsung-soc@vger.kernel.org, bhelgaas@google.com, linux-amlogic@lists.infradead.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jingoohan1@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, svarbanov@mm-sol.com, kernel@pengutroni x.de, gustavo.pimentel@synopsys.com, shawnguo@kernel.org, l.stach@pengutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On 2020-09-29 14:22, Jon Hunter wrote: > Hi Jisheng, > > On 29/09/2020 11:48, Jisheng Zhang wrote: >> Hi Jon, >> >> On Fri, 25 Sep 2020 09:53:45 +0100 Jon Hunter wrote: >> >>> >>> On 24/09/2020 12:05, Jisheng Zhang wrote: >>>> Improve the msi code: >>>> 1. Add proper error handling. >>>> 2. Move dw_pcie_msi_init() from each users to designware host to >>>> solve >>>> msi page leakage in resume path. >>> >>> Apologies if this is slightly off topic, but I have been meaning to >>> ask >>> about MSIs and PCI. On Tegra194 which uses the DWC PCI driver, >>> whenever we >>> hotplug CPUs we see the following warnings ... >>> >>> [ 79.068351] WARNING KERN IRQ70: set affinity failed(-22). >>> [ 79.068362] WARNING KERN IRQ71: set affinity failed(-22). >>> >> >> I tried to reproduce this issue on Synaptics SoC, but can't reproduce >> it. >> Per my understanding of the code in kernel/irq/cpuhotplug.c, this >> warning >> happened when we migrate irqs away from the offline cpu, this >> implicitly >> implies that before this point the irq has bind to the offline cpu, >> but how >> could this happen given current dw_pci_msi_set_affinity() >> implementation >> always return -EINVAL > > By default the smp_affinity should be set so that all CPUs can be > interrupted ... > > $ cat /proc/irq/70/smp_affinity > 0xff > > In my case there are 8 CPUs and so 0xff implies that the interrupt can > be triggered on any of the 8 CPUs. > > Do you see the set_affinity callback being called for the DWC irqchip > in > migrate_one_irq()? The problem is common to all MSI implementations that end up muxing all the end-point MSIs into a single interrupt. With these systems, you cannot set the affinity of individual MSIs (they don't target a CPU, they target another interrupt... braindead). Only the mux interrupt can have its affinity changed. So returning -EINVAL is the right thing to do. M. -- Jazz is not dead. It just smells funny...