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Subject: Re: [PATCH] ARM: tegra: Populate OPP table for Tegra20 Ventana
To:     Dmitry Osipenko <digetx@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Thierry Reding <thierry.reding@gmail.com>
CC:     <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
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References: <20201111103847.152721-1-jonathanh@nvidia.com>
 <7e40cd3e-7c34-c9a9-bf00-ba7d507a2d6b@gmail.com>
From:   Jon Hunter <jonathanh@nvidia.com>
Message-ID: <fb615118-ecf7-3092-9e50-2a8d72c1efcd@nvidia.com>
Date:   Wed, 11 Nov 2020 14:42:18 +0000
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On 11/11/2020 13:47, Dmitry Osipenko wrote:
> 11.11.2020 13:38, Jon Hunter =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>> Commit 9ce274630495 ("cpufreq: tegra20: Use generic cpufreq-dt driver
>> (Tegra30 supported now)") update the Tegra20 CPUFREQ driver to use the
>> generic CPUFREQ device-tree driver. Since this change CPUFREQ support
>> on the Tegra20 Ventana platform has been broken because the necessary
>> device-tree nodes with the operating point information are not populated
>> for this platform. Fix this by updating device-tree for Venata to
>> include the operating point informration for Tegra20.
>>
>> Fixes: 9ce274630495 ("cpufreq: tegra20: Use generic cpufreq-dt driver (T=
egra30 supported now)")
>> Cc: stable@vger.kernel.org
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>>  arch/arm/boot/dts/tegra20-ventana.dts | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/t=
egra20-ventana.dts
>> index b158771ac0b7..055334ae3d28 100644
>> --- a/arch/arm/boot/dts/tegra20-ventana.dts
>> +++ b/arch/arm/boot/dts/tegra20-ventana.dts
>> @@ -3,6 +3,7 @@
>> =20
>>  #include <dt-bindings/input/input.h>
>>  #include "tegra20.dtsi"
>> +#include "tegra20-cpu-opp.dtsi"
>> =20
>>  / {
>>  	model =3D "NVIDIA Tegra20 Ventana evaluation board";
>> @@ -592,6 +593,16 @@ clk32k_in: clock@0 {
>>  		#clock-cells =3D <0>;
>>  	};
>> =20
>> +	cpus {
>> +		cpu0: cpu@0 {
>> +			operating-points-v2 =3D <&cpu0_opp_table>;
>> +		};
>> +
>> +		cpu@1 {
>> +			operating-points-v2 =3D <&cpu0_opp_table>;
>> +		};
>> +	};
>> +
>>  	gpio-keys {
>>  		compatible =3D "gpio-keys";
>> =20
>>
>=20
> This could be wrong to do because CPU voltage is fixed to 1000mV in
> Ventana's DT, are you sure that higher clock rates don't require higher
> voltages? What is the CPU process ID and SoC speedo ID on Ventana?

I looked at that and I did not see any voltage scaling being done with
the previous version of the CPUFREQ driver on Ventana. I will double
check but if it should be then I guess that was broken before.

> You could easily hook up CPU voltage scaling, please see acer-500 DT and
> patch [1] for examples of how to set up regulators in DT. But then it
> shouldn't be a stable patch.

That assumes that you are in the same country as the board you are
testing on :-)

I went back and verified that CPUFREQ scaling is working on stable
kernels 4.4, 4.9, 4.14, 4.19 and 5.4 on Ventana. It is only after your
change that it no longer works and yes it should be in stable.

Jon

--=20
nvpublic