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From: Manish Narani <manish.narani@xilinx.com>
To: <gregkh@linuxfoundation.org>, <robh+dt@kernel.org>,
	<michal.simek@xilinx.com>, <balbi@kernel.org>,
	<p.zabel@pengutronix.de>
Cc: <git@xilinx.com>, <linux-usb@vger.kernel.org>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	Manish Narani <manish.narani@xilinx.com>
Subject: [RESEND PATCH v3 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller
Date: Tue, 15 Dec 2020 12:24:50 +0530	[thread overview]
Message-ID: <1608015291-52007-2-git-send-email-manish.narani@xilinx.com> (raw)
In-Reply-To: <1608015291-52007-1-git-send-email-manish.narani@xilinx.com>

Add documentation for Versal DWC3 controller. Add required property
'reg' for the same. Also add optional properties for snps,dwc3.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/usb/dwc3-xilinx.txt     | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
index 4aae5b2cef56..0629f48cc807 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
@@ -1,7 +1,8 @@
 Xilinx SuperSpeed DWC3 USB SoC controller
 
 Required properties:
-- compatible:	Should contain "xlnx,zynqmp-dwc3"
+- compatible:	May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
+- reg:		Base address and length of the register control block
 - clocks:	A list of phandles for the clocks listed in clock-names
 - clock-names:	Should contain the following:
   "bus_clk"	 Master/Core clock, have to be >= 125 MHz for SS
@@ -13,12 +14,22 @@ Required child node:
 A child node must exist to represent the core DWC3 IP block. The name of
 the node is not important. The content of the node is defined in dwc3.txt.
 
+Optional properties for snps,dwc3:
+- dma-coherent:	Enable this flag if CCI is enabled in design. Adding this
+		flag configures Global SoC bus Configuration Register and
+		Xilinx USB 3.0 IP - USB coherency register to enable CCI.
+- interrupt-names: Should contain the following:
+  "dwc_usb3"	USB gadget mode interrupts
+  "otg"		USB OTG mode interrupts
+  "hiber"	USB hibernation interrupts
+
 Example device node:
 
 		usb@0 {
 			#address-cells = <0x2>;
 			#size-cells = <0x1>;
 			compatible = "xlnx,zynqmp-dwc3";
+			reg = <0x0 0xff9d0000 0x0 0x100>;
 			clock-names = "bus_clk" "ref_clk";
 			clocks = <&clk125>, <&clk125>;
 			ranges;
@@ -26,7 +37,9 @@ Example device node:
 			dwc3@fe200000 {
 				compatible = "snps,dwc3";
 				reg = <0x0 0xfe200000 0x40000>;
-				interrupts = <0x0 0x41 0x4>;
+				interrupt-names = "dwc_usb3", "otg", "hiber";
+				interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
 				dr_mode = "host";
+				dma-coherent;
 			};
 		};
-- 
2.17.1


  reply	other threads:[~2020-12-15  6:57 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-15  6:54 [RESEND PATCH v3 0/2] Add a separate DWC3 OF driver for Xilinx platforms Manish Narani
2020-12-15  6:54 ` Manish Narani [this message]
2020-12-15  6:54 ` [RESEND PATCH v3 2/2] usb: dwc3: Add " Manish Narani
2020-12-21 18:05   ` Michael Tretter
2021-01-18 13:42   ` Michael Grzeschik
2021-01-18 15:24     ` Felipe Balbi
2021-01-19 16:39       ` Michael Grzeschik
2021-01-22  8:08     ` Michael Grzeschik
2021-01-22 13:06       ` Manish Narani
2021-01-22 13:34         ` Michael Grzeschik
2021-01-27 23:36           ` Michael Grzeschik
2021-02-08 23:56             ` Michael Grzeschik
2021-02-09  6:01               ` Manish Narani
2021-02-09 20:02                 ` Michael Grzeschik
2021-02-10 12:07                   ` Michael Grzeschik
2021-02-22 15:31   ` Michael Grzeschik
2021-02-25 11:41     ` Manish Narani

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