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[85.230.190.116]) by smtp.gmail.com with ESMTPSA id f1sm3344263ljk.86.2019.07.01.08.29.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Jul 2019 08:29:48 -0700 (PDT) Received: from johan by xi.terra with local (Exim 4.92) (envelope-from ) id 1hhyFS-00012l-KI; Mon, 01 Jul 2019 17:29:43 +0200 Date: Mon, 1 Jul 2019 17:29:42 +0200 From: Johan Hovold To: Charles Yeh Cc: Johan Hovold , Greg KH , linux-usb@vger.kernel.org, =?utf-8?B?WWVoLkNoYXJsZXMgW+iRieamrumRq10=?= Subject: Re: [PATCH] [PATCH v6] USB: serial: pl2303: Add new PID to support PL2303HXN (TYPE_HXN) Message-ID: <20190701152942.GA3787@localhost> References: <20190701122114.2952-1-charlesyeh522@gmail.com> <20190701133233.GI27333@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org On Mon, Jul 01, 2019 at 11:11:02PM +0800, Charles Yeh wrote: > > > + if (spriv->quirks & PL2303_QUIRK_LEGACY) { > > > + pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, > > > + 0x40); > > > > No need to break this line even if you end up with slightly more than 80 > > chars. > > > OK. I will ignore "WARNING: line over 80 characters". Yeah, it's ok to go slightly above 80 chars when it improves readability. > > > + } else if (spriv->type == &pl2303_type_data[TYPE_HXN]) { > > > + pl2303_update_reg(serial, PL2303_HXN_FLOWCTRL, > > > + PL2303_HXN_FLOWCTRL_MASK, > > > + PL2303_HXN_CTRL_RTS_CTS); > > > > Again, continuation lines should be indented at least two tabs further > > (you only use one tab now). > > > > I have done it the way you do today...but after checking > ./scripts/checkpatch.pl.. I got another warning message... > So I am a little confused now... > Previously before submitting.. must first pass ./scripts/checkpatch.pl > check. No ERROR, or WARRING message... > > I will return to the office tomorrow ... I will post another warning > message (according to the way you mentioned) checkpatch isn't always right. Just remember to indent continuation lines at least two tabs further, such as pl2303_update_reg(serial, PL2303_HXN_FLOWCTRL, PL2303_HXN_FLOWCTRL_MASK, PL2303_HXN_CTRL_RTS_CTS); > > } else if (spriv->type == &pl2303_type_data[TYPE_HXN]) { > > > > > + pl2303_vendor_write(serial, PL2303_HXN_RESET_CONTROL, > > > + 0); > > > > You again completely ignored my question about why you're wring 0 > > instead of 3 here. > > > > I'll ignore your patch until you explain. > > 3. In pl2303_open: Because TYPE_HXN is different from the instruction of reset > down/up stream used by TYPE_HX. > Therefore, we will also execute different instructions here. > The default of chip Reset Control is 0xFF(TYPE_HXN), therefore we will > write 0x00 to reset down/up stream(TYPE_HXN). I'm asking why you write the value 0 instead of 3 (or say, 0xfc)? Your documentation said bit 0 and 1 are used to reset the up and downstream pipes. To be more specific; what happens if I 1. set bit 0 2. clear bit 0? and leave the other bits alone (write back the same value, e.g. 0xfe). Johan