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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: stable@vger.kernel.org
Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-omap@vger.kernel.org, linux-i2c@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-mtd@lists.infradead.org
Subject: [BACKPORT 4.14.y 08/18] mtd: spi-nor: cadence-quadspi: add a delay in write sequence
Date: Thu,  5 Sep 2019 10:17:49 -0600	[thread overview]
Message-ID: <20190905161759.28036-9-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20190905161759.28036-1-mathieu.poirier@linaro.org>

From: Vignesh R <vigneshr@ti.com>

commit 61dc8493bae9ba82a1c72edbc6c6065f6a94456a upstream

As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this and set this flag for TI 66AK2G SoC.

[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index f22dd34f4f83..ff4edf4bb23c 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -38,6 +38,9 @@
 #define CQSPI_NAME			"cadence-qspi"
 #define CQSPI_MAX_CHIPSELECT		16
 
+/* Quirks */
+#define CQSPI_NEEDS_WR_DELAY		BIT(0)
+
 struct cqspi_st;
 
 struct cqspi_flash_pdata {
@@ -76,6 +79,7 @@ struct cqspi_st {
 	u32			fifo_depth;
 	u32			fifo_width;
 	u32			trigger_address;
+	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 };
 
@@ -623,6 +627,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
 	reinit_completion(&cqspi->transfer_complete);
 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
 	       reg_base + CQSPI_REG_INDIRECTWR);
+	/*
+	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+	 * Controller programming sequence, couple of cycles of
+	 * QSPI_REF_CLK delay is required for the above bit to
+	 * be internally synchronized by the QSPI module. Provide 5
+	 * cycles of delay.
+	 */
+	if (cqspi->wr_delay)
+		ndelay(cqspi->wr_delay);
 
 	while (remaining > 0) {
 		size_t write_words, mod_bytes;
@@ -1184,6 +1197,7 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	struct resource *res;
 	struct resource *res_ahb;
+	unsigned long data;
 	int ret;
 	int irq;
 
@@ -1241,6 +1255,10 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+	data  = (unsigned long)of_device_get_match_data(dev);
+	if (data & CQSPI_NEEDS_WR_DELAY)
+		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+						   cqspi->master_ref_clk_hz);
 
 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
 			       pdev->name, cqspi);
@@ -1312,7 +1330,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
 #endif
 
 static const struct of_device_id cqspi_dt_ids[] = {
-	{.compatible = "cdns,qspi-nor",},
+	{
+		.compatible = "cdns,qspi-nor",
+		.data = (void *)0,
+	},
+	{
+		.compatible = "ti,k2g-qspi",
+		.data = (void *)CQSPI_NEEDS_WR_DELAY,
+	},
 	{ /* end of table */ }
 };
 
-- 
2.17.1


  parent reply	other threads:[~2019-09-05 16:19 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-05 16:17 [BACKPORT 4.14.y 00/18] Backport candidate from TI 4.14 product kernel Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 01/18] PCI: designware-ep: Fix find_first_zero_bit() usage Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 02/18] PCI: dra7xx: Fix legacy INTD IRQ handling Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 03/18] drm/omap: panel-dsi-cm: fix driver Mathieu Poirier
2019-09-10 14:34   ` Greg KH
2019-09-11 11:48     ` Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 04/18] usb: dwc3: Allow disabling of metastability workaround Mathieu Poirier
2019-09-10 14:36   ` Greg KH
2019-09-11 14:01     ` Mathieu Poirier
2019-11-11  9:16       ` Greg KH
2019-09-05 16:17 ` [BACKPORT 4.14.y 05/18] mfd: palmas: Assign the right powerhold mask for tps65917 Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 06/18] ASoC: tlv320aic31xx: Handle inverted BCLK in non-DSP modes Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 07/18] mtd: spi-nor: enable 4B opcodes for mx66l51235l Mathieu Poirier
2019-09-05 16:17 ` Mathieu Poirier [this message]
2019-09-05 16:17 ` [BACKPORT 4.14.y 09/18] misc: pci_endpoint_test: Prevent some integer overflows Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 10/18] PCI: dra7xx: Add shutdown handler to cleanly turn off clocks Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 11/18] misc: pci_endpoint_test: Fix BUG_ON error during pci_disable_msi() Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 12/18] mailbox: reset txdone_method TXDONE_BY_POLL if client knows_txdone Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 13/18] ASoC: tlv320dac31xx: mark expected switch fall-through Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 14/18] ASoC: davinci-mcasp: Handle return value of devm_kasprintf Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 15/18] ASoC: davinci: Kill BUG_ON() usage Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 16/18] ASoC: davinci-mcasp: Fix an error handling path in 'davinci_mcasp_probe()' Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 17/18] i2c: omap: Trigger bus recovery in lockup case Mathieu Poirier
2019-09-05 16:17 ` [BACKPORT 4.14.y 18/18] cpufreq: ti-cpufreq: add missing of_node_put() Mathieu Poirier
2019-09-05 16:24 ` [BACKPORT 4.14.y 00/18] Backport candidate from TI 4.14 product kernel Wolfram Sang

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