On Wed, Oct 09, 2019 at 06:39:00PM -0500, Rob Herring wrote:
> On Wed, Oct 09, 2019 at 10:43:41AM +0800, JC Kuo wrote:
> > Extend the bindings to cover the set of features found in Tegra194.
> > Note that, technically, there are four more supplies connected to the
> > XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
> > , but the power sequencing requirements of Tegra194 require these to be
> > under the control of the PMIC.
> > 
> > Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is
> > possible for some platforms have long signal trace that could not
> > provide sufficient electrical environment for Gen 2 speed. To deal with
> > this, a new device node property "nvidia,disable-gen2" was added to
> > Tegra194 that be used to specifically disable Gen 2 speed for a
> > particular USB 3.0 port so that the port can be limited to Gen 1 speed
> > and avoid the instability.
> 
> I suspect this may be a common issue and we should have a common 
> property. Typically, this kind of property is in the controller though 
> and supports multiple speed limits. See PCI bindings for inspiration.

Given that support for gen 2 speeds is dependent on signal trace length,
it doesn't really make sense to restrict the whole controller to a given
speed if only the signal trace for a single port exceeds the limit for
which gen 2 would work.

Also, the USB PHYs are in a different hardware block than the USB
controller, so this really is a property of the PHY block, not the USB
controller.

Thierry