From: JC Kuo <jckuo@nvidia.com>
To: <gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>,
<robh@kernel.org>, <jonathanh@nvidia.com>, <kishon@ti.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-usb@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<nkristam@nvidia.com>, JC Kuo <jckuo@nvidia.com>,
Thierry Reding <treding@nvidia.com>
Subject: [PATCH v4 02/16] clk: tegra: Don't enable PLLE HW sequencer at init
Date: Fri, 16 Oct 2020 21:07:12 +0800 [thread overview]
Message-ID: <20201016130726.1378666-3-jckuo@nvidia.com> (raw)
In-Reply-To: <20201016130726.1378666-1-jckuo@nvidia.com>
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
v4:
no change
v3:
no change
drivers/clk/tegra/clk-pll.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index c5cc0a2dac6f..0193cebe8c5a 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
pll_writel(val, PLLE_SS_CTRL, pll);
udelay(1);
- val = pll_readl_misc(pll);
- val &= ~PLLE_MISC_IDDQ_SW_CTRL;
- pll_writel_misc(val, pll);
-
- val = pll_readl(pll->params->aux_reg, pll);
- val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
- val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
- pll_writel(val, pll->params->aux_reg, pll);
- udelay(1);
- val |= PLLE_AUX_SEQ_ENABLE;
- pll_writel(val, pll->params->aux_reg, pll);
-
out:
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
--
2.25.1
next prev parent reply other threads:[~2020-10-16 13:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-16 13:07 [PATCH v4 00/16] Tegra XHCI controller ELPG support JC Kuo
2020-10-16 13:07 ` [PATCH v4 01/16] clk: tegra: Add PLLE HW power sequencer control JC Kuo
2020-10-16 13:07 ` JC Kuo [this message]
2020-10-16 13:07 ` [PATCH v4 03/16] phy: tegra: xusb: Move usb3 port init for Tegra210 JC Kuo
2020-10-16 13:07 ` [PATCH v4 04/16] phy: tegra: xusb: tegra210: Do not reset UPHY PLL JC Kuo
2020-10-16 13:07 ` [PATCH v4 05/16] phy: tegra: xusb: Rearrange UPHY init on Tegra210 JC Kuo
2020-10-16 13:07 ` [PATCH v4 06/16] phy: tegra: xusb: Add Tegra210 lane_iddq operation JC Kuo
2020-10-16 13:07 ` [PATCH v4 07/16] phy: tegra: xusb: Add sleepwalk and suspend/resume JC Kuo
2020-10-16 13:07 ` [PATCH v4 08/16] soc/tegra: pmc: Provide USB sleepwalk register map JC Kuo
2020-10-16 13:07 ` [PATCH v4 09/16] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop JC Kuo
2020-10-16 13:07 ` [PATCH v4 10/16] dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop JC Kuo
2020-10-19 21:40 ` Rob Herring
2020-10-28 9:18 ` JC Kuo
2020-11-13 16:20 ` Thierry Reding
2020-11-19 5:28 ` JC Kuo
2020-10-16 13:07 ` [PATCH v4 11/16] phy: tegra: xusb: Add wake/sleepwalk for Tegra210 JC Kuo
2020-10-16 13:07 ` [PATCH v4 12/16] phy: tegra: xusb: Tegra210 host mode VBUS control JC Kuo
2020-10-16 13:07 ` [PATCH v4 13/16] phy: tegra: xusb: Add wake/sleepwalk for Tegra186 JC Kuo
2020-10-16 13:07 ` [PATCH v4 14/16] arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq JC Kuo
2020-10-16 13:07 ` [PATCH v4 15/16] usb: host: xhci-tegra: Unlink power domain devices JC Kuo
2020-10-16 13:07 ` [PATCH v4 16/16] xhci: tegra: Enable ELPG for runtime/system PM JC Kuo
2020-10-27 6:10 ` kernel test robot
2020-11-13 16:44 ` [PATCH v4 00/16] Tegra XHCI controller ELPG support Thierry Reding
2020-11-17 6:14 ` JC Kuo
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